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ORCID16th LATS 2015: Puerto Vallarta, Mexico
- 16th Latin-American Test Symposium, LATS 2015, Puerto Vallarta, Mexico, March 25-27, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-6710-3
- Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. 1
Session 1: Fault Modelling and Simulation
- Davide Ferraretto, Graziano Pravadelli
:
Efficient fault injection in QEMU. 1-6 - Hiroyuki Yamauchi, Worawit Somha:
Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs. 1-6 - Jaak Kousaar, Raimund Ubar, Igor Aleksejev:
Complex delay fault reasoning with sequential 7-valued algebra. 1-6
Session 2: Automatic Test Generation
- Alexandra Kourfali, Dirk Stroobandt:
Test set generation almost for free using a run-time FPGA reconfiguration technique. 1-6 - N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls:
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. 1-6 - Riccardo Cantoro, Marco Gaudesi, Ernesto Sánchez, Pasquale Davide Schiavone, Giovanni Squillero:
An evolutionary approach for test program compaction. 1-6
Session 3: Analog Mixed Signal Test
- Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
A digital technique for the evaluation of SSB phase noise of analog/RF signals. 1-6 - Carlos Viale, Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Carlos Daniel Vázquez:
Single event effects in an analog SOI transconductor: a case study. 1-4 - Rigoberto Bracamontes-Salazar, Esdras Juárez-Hernández, Federico Lobato-Lopez, Esteban Martinez Guerrero:
CMOS amplifier with self-correction offset for SerDes applications. 1-4
Session 4: Design for Testability
- Yu-Wei Lee, Nur A. Touba:
Improving logic obfuscation via logic cone analysis. 1-6 - Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin:
Virtual reconfigurable scan-chains on FPGAs for optimized board test. 1-6 - Alexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero:
A controllable setup and propagation delay flip-flop design. 1-5
Session 5: Memory: Testing and Fault Injection
- Paolo Bernardi, Lyl M. Ciganda Brasca, Matteo Sonza Reorda, Said Hamdioui:
SW-based transparent in-field memory testing. 1-6 - Jimmy Tarrillo, Jorge L. Tonfat, Lucas A. Tambara, Fernanda Lima Kastensmidt, Ricardo Reis:
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments. 1-6
Session 6: System-on-Chip Test
- Sandeep Kumar Singh, Abir J. Mondal, Alak Majumder:
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs. 1-6 - Andres F. Gomez, Víctor H. Champac:
Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. 1-6 - Baohu Li, Bei Zhang, Vishwani D. Agrawal:
Adopting multi-valued logic for reduced pin-count testing. 1-6
Poster Session
- Mafalda Cortez, Said Hamdioui, Ryoichi Ishihara:
Design dependent SRAM PUF robustness analysis. 1-6 - Jailene Hernandez, Johan Castrillon, Manuel Jiménez, Angel De La Torre, Pedro Escalona, Rogelio Palomera:
A virtual instrument design for low-cost charge-pumping characterization of integrated MOSFETs. 1-4 - Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra:
FPGA redundancy recovery based on partial bitstreams for multiple partitions. 1-4 - Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver. 1-4 - Guimao Zhang, Maoxiang Yi, Yong Miao, Dawen Xu, Huaguo Liang:
NBTI-induced circuit aging optimization by protectability-aware gate replacement technique. 1-4
Special Session: Issues in Electronic Design Automation: Tolerance Analysis and Design Verification
- Luis Gerardo de la Fraga, Esteban Tlelo-Cuautle:
Optimizing operational amplifiers by metaheuristics and considering tolerance analysis. 1-4 - Ivick Guerra-Gómez, Trent McConaghy, Esteban Tlelo-Cuautle:
Study of regression methodologies on analog circuit design. 1-6 - Hosoon Shin, Sheldon X.-D. Tan, Guoyong Shi, Esteban Tlelo-Cuautle:
Rare event diagnosis by iterative failure region locating and elite learning sample selection. 1-5 - Jesus Lopez-Arredondo, Esteban Tlelo-Cuautle, Rodolfo Trejo-Guerra:
Optimizing an LDO voltage regulator by evolutionary algorithms considering tolerances of the circuit elements. 1-5 - J. L. Bueno-Ruiz, C. A. Arriaga-Arriaga, R. Huerta-Barrera, G. V. Cruz-Dominguez, C. H. Pimentel-Romero, Jesús M. Muñoz-Pacheco, Luz del Carmen Gómez-Pavón, Olga Guadalupe Félix-Beltrán, Arnulfo Luis-Ramos:
Fault conditions of a simple chaotic circuit under capacitor nonlinear effects. 1-5
Session 7: Software-Based Fault Tolerance
- Sebastian Müller, Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus, Mario Schölzel:
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. 1-6 - Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Fernanda Lima Kastensmidt:
Considerations on application of selective hardening based on software fault tolerance techniques. 1-6
Session 8: Built-In Self-Test
- Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test compression for circuits with multiple scan chains. 1-6 - Xian Wang, Kenfack Blanchard, Estella Silva, Abhijit Chatterjee:
"Safe" built-in test and tuning of boost converters using feedback loop perturbations. 1-6 - Takanori Moriyasu, Satoshi Ohtake:
A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults. 1-6
Session 9: Issues in EMC, EMI and Radiation
- Karine Coulié-Castellani, Wenceslas Rahajandraibe, Hassen Aziza, Jean-Michel Portal, Gilles Micolau:
Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment. 1-5 - J. Rafael del-Rey, Zabdiel Brito-Brito, José Ernesto Rayas-Sánchez:
Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect. 1-5 - João Guilherme Mourão Melo, Frank Sill Torres:
Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors. 1-6 - Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura, Víctor H. Champac:
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. 1-6
Session 10: Design Verification and Validation
- Antonio Zenteno Ramírez:
Power distribution network analysis using semi irregular plane shape approach and via modeling. 1-6 - Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang:
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. 1-6 - André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Vericonn: a tool to generate efficient interconnection networks for post-silicon debug. 1-6 - Bharath Shivashankar, Michael Skaggs, Sushmita Kadiyala Rao, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Estimation of dynamic current waveforms using pre-characterization of standard cells. 1-6 - Zissis Poulos, Andreas G. Veneris:
Exemplar-based failure triage for regression design debugging. 1-6
Session 11: Fault Tolerance Architectures
- Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt:
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. 1-6 - Carlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Fault-tolerance in FPGA focusing power reduction or performance enhancement. 1-6 - Ronaldo Rodrigues Ferreira, Ernesto Sánchez, Jean da Rolt, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro, Matteo Sonza Reorda:
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture. 1-6 - Thiago Copetti, G. Cardoso Medeiros, Letícia Maria Bolzani Poehls, Fabian Vargas:
NBTI-aware design of integrated circuits: a hardware-based approach. 1-6 - Adit D. Singh:
Scan based two-pattern tests: should they target opens instead of TDFs? 1-2 - Grégoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza:
Design of ultra-low-power smart wearable systems. 1-2 - Matteo Sonza Reorda:
In-field test of safety-critical systems: is functional test a feasible solution? 1-2
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