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ORCIDMadhu Mutyam
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- affiliation: Indian Institute of Technology Madras, Department of Computer Science and Engineering, India
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2020 – today
- 2024
[c47]Abdun Nihaal
, Madhu Mutyam:
Selective Memory Compression for GPU Memory Oversubscription Management. ICPP 2024: 189-198- [c46]Praseetha M, Madhu Mutyam, Venkata Kalyan Tavva:
Cache Line Pinning for Mitigating Row Hammer Attack. ICPP 2024: 802-811 - 2023
- [j32]Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2766-2770 (2023) - 2020
- [j31]Praveen Alapati, Madhu Mutyam, Swamy Saranam:
Concurrent Treaps and Impact of Locking Objects. New Gener. Comput. 38(1): 187-212 (2020) - [j30]S. R. Swamy Saranam Chongala, Sumitha George, Hariram Thirucherai Govindarajan, Jagadish Kotra, Madhu Mutyam, John Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan:
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3881-3892 (2020) - [j29]Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam:
A Scalable and Energy-Efficient Concurrent Binary Search Tree With Fatnodes. IEEE Trans. Sustain. Comput. 5(4): 468-484 (2020) - [c45]Joe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam:
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. ICCD 2020: 239-246 - [c44]Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
Fuzzy fairness controller for NVMe SSDs. ICS 2020: 22:1-22:12
2010 – 2019
- 2019
- [j28]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop:
Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. 24(2): 20:1-20:23 (2019) - [c43]Sayantan Ray, Madhu Mutyam:
POSTER: Variable Sized Cache-Block Compaction. PACT 2019: 471-472 - [c42]Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam:
Post-Model Validation of Victim DRAM Caches. ICCD 2019: 305-308 - [c41]Puneet Saraf, Madhu Mutyam:
Endurance enhancement of write-optimized STT-RAM caches. MEMSYS 2019: 101-113 - 2018
- [j27]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam:
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. IEEE Comput. Archit. Lett. 17(2): 213-216 (2018) - [j26]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop:
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2485-2496 (2018) - [c40]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan:
CAMO: A novel cache management organization for GPGPUs. ASP-DAC 2018: 215-220 - [c39]S. R. Swamy Saranam, Madhu Mutyam:
TDC: Tagless DRAM Cache. ISVLSI 2018: 88-93 - 2017
- [j25]Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam:
MBZip: Multiblock Data Compression. ACM Trans. Archit. Code Optim. 14(4): 42:1-42:29 (2017) - [c38]Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam:
FatCBST: Concurrent Binary Search Tree with Fatnodes. HPCC/SmartCity/DSS 2017: 356-363 - [c37]Praveen Alapati, Swamy Saranam, Madhu Mutyam:
Concurrent Treaps. ICA3PP 2017: 776-790 - [c36]Dennis Antony Varkey, Biswabandan Panda, Madhu Mutyam:
RCTP: Region Correlated Temporal Prefetcher. ICCD 2017: 73-80 - [c35]Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. VLSID 2017: 35-40 - 2016
- [j24]Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam:
PBC: Prefetched Blocks Compaction. IEEE Trans. Computers 65(8): 2534-2547 (2016) - [c34]Gnaneswara Rao Jonna, Vamana Murthi Thuniki, Madhu Mutyam:
CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router. ARCS 2016: 35-47 - 2015
- [j23]Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam:
SkipCache: application aware cache management for chip multi-processors. IET Comput. Digit. Tech. 9(6): 293-299 (2015) - 2014
- [j22]Venkata Kalyan Tavva, Ravi Kasha, Madhu Mutyam:
EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices. ACM Trans. Archit. Code Optim. 11(3): 31:1-31:26 (2014) - [j21]John Jose, Madhu Mutyam:
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. ACM Trans. Design Autom. Electr. Syst. 19(4): 35:1-35:22 (2014) - [c33]Sudharsan Jagathrakshakan, Venkata Kalyan Tavva, Madhu Mutyam:
Data remapping for an energy efficient burst chop in DRAM memory systems. PACT 2014: 507-508 - [c32]T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam:
Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time. ASP-DAC 2014: 598-603 - [c31]Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam:
SAMO: store aware memory optimizations. Conf. Computing Frontiers 2014: 33:1-33:10 - [c30]Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam:
Minimally buffered single-cycle deflection router. DATE 2014: 1-4 - [c29]Pritam Majumder, T. Venkata Kalyan, Madhu Mutyam:
SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. ICCD 2014: 104-109 - [c28]Prasanna Venkatesh Rengasamy, Madhu Mutyam:
Using packet information for efficient communication in NoCs. NOCS 2014: 143-150 - 2013
- [j20]Arpit Joshi, Prasanna Venkatesh Rengasamy, Madhu Mutyam:
Prevention slot flow-control mechanism for low latency torus network-on-chip. IET Comput. Digit. Tech. 7(6): 304-316 (2013) - [c27]Tripti S. Warrier, B. Anupama, Madhu Mutyam:
An Application-Aware Cache Replacement Policy for Last-Level Caches. ARCS 2013: 207-219 - [c26]John Jose, Bhawna Nayak, Damarla Kranthi Kumar, Madhu Mutyam:
DeBAR: deflection based adaptive router with minimal buffering. DATE 2013: 1583-1588 - [c25]Bhawna Nayak, John Jose, Madhu Mutyam:
SLIDER: Smart Late Injection DEflection Router for mesh NoCs. ICCD 2013: 377-383 - 2012
- [j19]Madhu Mutyam:
Fibonacci Codes for Crosstalk Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1899-1903 (2012) - [c24]Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam:
SkipCache: miss-rate aware cache management. PACT 2012: 481-482 - [c23]John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam:
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. ICCAD 2012: 564-568 - [c22]C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam:
Way Sharing Set Associative Cache Architecture. VLSI Design 2012: 251-256 - 2011
- [j18]Kartikey Mittal, Arpit Joshi, Madhu Mutyam:
Timing variation-aware scheduling and resource binding in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 16(4): 40:1-40:19 (2011) - [c21]John Jose, J. Shiva Shankar, K. V. Mahathi, Damarla Kranthi Kumar, Madhu Mutyam:
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. NoCArc@MICRO 2011: 23-28 - [c20]Arpit Joshi, Madhu Mutyam:
Prevention flow-control for low latency torus networks-on-chip. NOCS 2011: 41-48
2000 – 2009
- 2009
- [j17]Nallamothu Satyanarayana, A. Vinaya Babu, Madhu Mutyam:
Delay-efficient bus encoding techniques. Microprocess. Microsystems 33(5-6): 365-373 (2009) - [j16]Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin:
Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58(7): 865-877 (2009) - [j15]Madhu Mutyam:
Selective shielding technique to eliminate crosstalk transitions. ACM Trans. Design Autom. Electr. Syst. 14(3): 43:1-43:20 (2009) - 2008
- [c19]Mohammed Abid Hussain, Madhu Mutyam:
Block remap with turnoff: A variation-tolerant cache design technique. ASP-DAC 2008: 783-788 - [c18]Kanakagiri Raghavendra, Madhu Mutyam:
Process Variation Aware Issue Queue Design. DATE 2008: 1438-1443 - [c17]Abu Saad Papa, Madhu Mutyam:
Power management of variation aware chip multiprocessors. ACM Great Lakes Symposium on VLSI 2008: 423-428 - [c16]T. Venkata Kalyan, Madhu Mutyam:
Word-interleaved cache: an energy efficient data cache architecture. ISLPED 2008: 265-270 - [c15]T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi:
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design 2008: 235-241 - 2007
- [c14]Madhu Mutyam, Narayanan Vijaykrishnan:
Working with process variation aware caches. DATE 2007: 1152-1157 - [c13]Madhu Mutyam:
Selective shielding: a crosstalk-free bus encoding technique. ICCAD 2007: 618-621 - [c12]Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Variation Analysis of CAM Cells. ISQED 2007: 333-338 - [c11]Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin:
Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI 2007: 375-382 - [c10]Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu:
Exploiting on-chip data behavior for delay minimization. SLIP 2007: 103-110 - 2006
- [j14]K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam:
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electron. 2(3): 425-436 (2006) - [c9]K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam:
Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI 2006: 119-122 - [c8]Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie:
Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360 - [c7]Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Compiler-directed thermal management for VLIW functional units. LCTES 2006: 163-172 - 2005
- [j13]Madhu Mutyam, Kamala Krithivasan, A. Siddhartha Reddy:
On Characterizing Recursively Enumerable Languages by Insertion Grammars. Fundam. Informaticae 64(1-4): 317-324 (2005) - [j12]Madhu Mutyam:
Rewriting P systems: improved hierarchies. Theor. Comput. Sci. 334(1-3): 161-175 (2005) - 2004
- [j11]Madhu Mutyam:
Descriptional Complexity of Rewriting P Systems. J. Autom. Lang. Comb. 9(2/3): 311-316 (2004) - [j10]Madhu Mutyam, Kamala Krithivasan:
Length Synchronization Context-Free Grammars. J. Autom. Lang. Comb. 9(4): 457-464 (2004) - [j9]Madhu Mutyam, Vaka Jaya Prakash, Kamala Krithivasan:
Rewriting Tissue P Systems. J. Univers. Comput. Sci. 10(9): 1250-1271 (2004) - [c6]P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam:
A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design 2004: 443-448 - [c5]Madhu Mutyam:
Preventing Crosstalk Delay using Fibonacci Representation. VLSI Design 2004: 685-688 - 2003
- [j8]Madhu Mutyam, Kamala Krithivasan:
On a class of P automata. Int. J. Comput. Math. 80(9): 1111-1120 (2003) - [j7]Madhu Mutyam:
Probabilistic Rewriting P Systems. Int. J. Found. Comput. Sci. 14(1): 157-166 (2003) - [j6]M. Sakthi Balan, Kamala Krithivasan, Madhu Mutyam:
Some Variants in Communication of Parallel Communicating Pushdown Automata. J. Autom. Lang. Comb. 8(3): 401-416 (2003) - [j5]Rodica Ceterchi, Madhu Mutyam, Gheorghe Paun, K. G. Subramanian:
Array-rewriting P systems. Nat. Comput. 2(3): 229-249 (2003) - 2002
- [j4]Madhu Mutyam, Kamala Krithivasan:
Generalized normal form for rewriting P systems. Acta Informatica 38(10): 721-734 (2002) - [j3]Madhu Mutyam, Kamala Krithivasan:
Improved Results about Universality of P systems. Bull. EATCS 76: 162-168 (2002) - [j2]Kamala Krithivasan, Madhu Mutyam:
Contextual P Systems. Fundam. Informaticae 49(1-3): 179-189 (2002) - [j1]Madhu Mutyam, Kamala Krithivasan:
A Note on Hybrid P Systems. Grammars 5(3): 239-244 (2002) - [c4]Madhu Mutyam:
Complexity Issues in Rewriting P Systems. DCFS 2002: 148-159 - [c3]Madhu Mutyam, Kamala Krithivasan:
A Survey of Some Variants of P Systems. WMC-CdeA 2002: 360-370 - 2001
- [c2]Madhu Mutyam, Kamala Krithivasan:
P Systems with Membrane Creation: Universality and Efficiency. MCU 2001: 276-287 - 2000
- [c1]Madhu Mutyam, Kamala Krithivasan:
Universality Results for Some Variants of P Systems. WMP 2000: 237-254
Coauthor Index
aka: Venkata Kalyan Tavva
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