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Thomas Steininger
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2010 – 2019
- 2010
- [c11]Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten:
TLM+ modeling of embedded HW/SW systems. DATE 2010: 75-80 - [c10]Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten:
Model reduction techniques for the formal verification of hardware dependent software. HLDVT 2010: 148-153
2000 – 2009
- 2009
- [b1]Thomas Steininger:
Automated assertion transformation across multiple abstraction levels. Technical University Munich, Germany, 2009, pp. 1-199 - 2007
- [c9]Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull:
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE 2007: 767-772 - [c8]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE 2007: 894-899 - [c7]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertion Refinement. IESS 2007: 1-14 - 2006
- [c6]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten:
Case Study on Transaction Level Modeling. FDL 2006: 209-215 - [c5]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit:
IP Library For Temporal SystemC Assertions. FDL 2006: 301-309 - [c4]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Specification Language for Transaction Level Assertions. HLDVT 2006: 77-84 - [c3]Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertions. ICCD 2006: 286-293 - 2004
- [c2]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi:
Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. ISORC 2004: 129-135 - [c1]Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger:
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. VLSI Design 2004: 577-
Coauthor Index
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