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ORCIDNadine Azémard
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- affiliation: LIRMM Montpellier, France
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2020 – today
- 2023
[j19]Corentin Delacour
, Stefania Carapezzi, Gabriele Boschetto, Madeleine Abernot, Thierry Gil, Nadine Azémard, Aida Todri-Sanial:
A mixed-signal oscillatory neural network for scalable analog computations in phase domain. Neuromorph. Comput. Eng. 3(3): 34004 (2023)- 2021
- [c39]Gwenael Chaillou, Philippe Maurine, Jean-Marc Gallière, Nadine Azémard:
Iterative Method for Performance Prediction Improvement of Integrated Circuits. DCIS 2021: 1-5 - [c38]Corentin Delacour, Stefania Carapezzi, Madeleine Abernot, Gabriele Boschetto, Nadine Azémard, Jérémie Salles, Thierry Gil, Aida Todri-Sanial:
Oscillatory Neural Networks for Edge AI Computing. ISVLSI 2021: 326-331
2010 – 2019
- 2019
- [i2]Abhishek Singh Dahiya, Jerome Thireau, Jamila Boudaden, Swatchith Lal, Umair Gulzar, Yan Zhang, Thierry Gil, Nadine Azémard, Peter Ramm, Tim Kiessling, Cian O'Murchu, Fredrik Sebelius, Jonas Tilly, Colm Glynn, Shane Geary, Colm O'Dwyer, Kafil Razeeb, Alain Lacampagne, Benoît Charlot, Aida Todri-Sanial:
Energy Autonomous Wearable Sensors for Smart Healthcare: A Review. CoRR abs/1912.02596 (2019) - 2018
- [c37]Rida Kheirallah, Jean-Marc Gallière, Nadine Azémard, Gilles R. Ducharme:
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. PATMOS 2018: 88-91 - 2017
- [c36]Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azémard, Aida Todri-Sanial:
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic. ICRC 2017: 1-6 - 2016
- [j18]Ricardo Reis, Nadine Azémard:
Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015. J. Low Power Electron. 12(1): 56-57 (2016) - [j17]Rida Kheirallah, Gilles R. Ducharme, Nadine Azémard:
Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices. J. Low Power Electron. 12(1): 58-63 (2016) - [c35]Jie Liang, Liuyang Zhang, Nadine Azémard-Crestani, Pascal Nouet, Aida Todri-Sanial:
Physical description and analysis of doped carbon nanotube interconnects. PATMOS 2016: 250-255 - 2015
- [j16]Nadine Azémard, Eugeni García-Moreno:
Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014. J. Low Power Electron. 11(2): 249 (2015) - 2014
- [j15]Nadine Azémard, Jörg Henkel:
Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013. J. Low Power Electron. 10(1): 116-117 (2014) - 2012
- [j14]Nadine Azémard, Marc Belleville:
Selected Articles from the VARI 2011 Workshop. J. Low Power Electron. 8(1): 82 (2012) - [j13]Nadine Azémard, Gilles Jacquemod:
Selected Articles from the VARI 2012 Workshop. J. Low Power Electron. 8(5): 696 (2012) - [j12]Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme:
Delay-correlation-aware SSTA based on conditional moments. Microelectron. J. 43(4): 263-273 (2012) - [c34]Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme:
Statistical timing characterization. ISSoC 2012: 1-4 - 2011
- [j11]Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard:
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. 42(5): 718-732 (2011) - 2010
- [j10]Nadine Azémard:
Selected Peer-Reviewed Articles from the VARI 2010 Workshop. J. Low Power Electron. 6(4): 563 (2010) - [j9]Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson:
On-Chip Process Variability Monitoring Flow. J. Low Power Electron. 6(4): 601-606 (2010)
2000 – 2009
- 2009
- [j8]V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine:
Timing margin evaluation with a simple statistical timing analysis flow. J. Embed. Comput. 3(3): 221-229 (2009) - [c33]Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme:
Interpreting SSTA Results with Correlation. PATMOS 2009: 16-25 - [c32]Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels:
Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS 2009: 247-255 - [c31]Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard:
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS 2009: 266-275 - 2008
- [j7]Nadine Azémard, Philippe Maurine, Johan Vounckx:
Editorial. Integr. 41(1): 1 (2008) - [c30]Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme:
SSTA considering switching process induced correlations. APCCAS 2008: 562-565 - [c29]Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard:
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321 - 2007
- [j6]B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 801-815 (2007) - [c28]B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Temperature and voltage aware timing analysis: application to voltage drops. DATE 2007: 1012-1017 - [c27]V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine:
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147 - [e2]Nadine Azémard, Lars J. Svensson:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Lecture Notes in Computer Science 4644, Springer 2007, ISBN 978-3-540-74441-2 [contents] - [i1]Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol. CoRR abs/0710.4760 (2007) - 2006
- [j5]Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine:
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integr. 39(4): 433-456 (2006) - [j4]B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1677-1684 (2006) - [c26]Robin Perrot, Nadine Azémard, Philippe Maurine:
Request-skip adders : CMOS standard cell data dependent adders. ICECS 2006: 510-513 - [c25]Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard:
Circuit sizing method under delay constraint. ISCAS 2006 - [c24]B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Timing analysis in presence of supply voltage and temperature variations. ISPD 2006: 10-16 - [c23]V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine:
Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476 - [e1]Johan Vounckx, Nadine Azémard, Philippe Maurine:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. Lecture Notes in Computer Science 4148, Springer 2006, ISBN 3-540-39094-4 [contents] - 2005
- [c22]Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645 - [c21]Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard:
Circuit optimization based on speed indicators. ICECS 2005: 1-4 - [c20]Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard:
Speed Indicators for Circuit Optimization. PATMOS 2005: 618-628 - [c19]B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Temperature Dependency in UDSM Process. PATMOS 2005: 693-703 - 2004
- [c18]Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192 - [c17]Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109 - [c16]B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118 - [c15]A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne:
Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731 - [c14]B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848 - 2003
- [c13]B. Lasbouygues, Joel Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Continuous representation of the performance of a CMOS library. ESSCIRC 2003: 595-598 - [c12]Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69 - [c11]Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460 - 2002
- [j3]Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne:
Transition time modeling in deep submicron CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1352-1363 (2002) - [c10]Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne:
Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330 - [c9]Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257 - 2001
- [j2]Nadine Azémard, Daniel Auvergne:
POPS: A tool for delay/power performance optimization. J. Syst. Archit. 47(3-4): 375-382 (2001) - [c8]Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312 - [c7]Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne:
Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335 - [c6]Nadine Azémard, M. Aline, Daniel Auvergne:
Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378
1990 – 1999
- 1999
- [c5]S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne:
Delay-power performance analysis. ICECS 1999: 1543-1546 - 1996
- [c4]S. Turgis, Nadine Azémard, Daniel Auvergne:
Design and selection of buffers for minimum power-delay product. ED&TC 1996: 224-229 - 1995
- [c3]S. Turgis, Nadine Azémard, Daniel Auvergne:
Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134 - 1993
- [j1]Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne:
Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1170-1177 (1993) - 1992
- [c2]Nadine Azémard, V. Bonzom, Daniel Auvergne:
P.SIZE: a sizing aid for optimized designs. EURO-DAC 1992: 160-165 - 1991
- [c1]Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert:
Formal sizing rules of CMOS circuits. EURO-DAC 1991: 96-100
Coauthor Index
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