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2020 – today
- 2024
[c70]Mohamed Naeim, Herman Oprins, Sudipta Das, Geert Van der Plas, Yun Dai, Pinhong Chen, CT Kao, Dwaipayan Biswas, Dragomir Milojevic:
Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC. ISVLSI 2024: 33-38- 2023
- [j40]Quentin Delhaye
, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic:
Impact of gate-level clustering on automated system partitioning of 3D-ICs. Microelectron. J. 139: 105896 (2023) - [c69]Mohamed Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic:
Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. 3DIC 2023: 1-4 - [c68]Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov:
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE 2023: 1-6 - [c67]Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert:
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS 2023: 1-7 - [i2]Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic:
Impact of gate-level clustering on automated system partitioning of 3D-ICs. CoRR abs/2307.09308 (2023) - 2022
- [j39]Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne:
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 661-665 (2022) - [j38]Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne:
Efficient Backside Power Delivery for High-Performance Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1748-1756 (2022) - [c66]Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne:
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. SLIP 2022: 3:1-3:5 - [c65]Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, N. Pinho, Tomas Webers, Dimitrios Velenis, A. Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke:
(Why do we need) Wireless Heterogeneous Integration (anyway?). VLSI Technology and Circuits 2022: 256-257 - [c64]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c63]Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne:
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - [c62]Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi:
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits 2022: 431-432 - 2021
- [c61]Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic:
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). SLIP 2021: 17-23 - [c60]Geert Van der Plas, Eric Beyne:
Design and Technology Solutions for 3D Integrated High Performance Systems. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c59]Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic:
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC 2019: 1-4 - [c58]Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne:
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC 2019: 1-6 - [c57]Gaspard Hiblot, Yefan Liu, Geert Hellings, Geert Van der Plas:
Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage. IRPS 2019: 1-5 - 2018
- [j37]Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne:
A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express 15(13): 20180460 (2018) - [c56]Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne, Kristof Croes:
TSV process-induced MOS reliability degradation. IRPS 2018: 5 - 2016
- [c55]C. Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne:
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. 3DIC 2016: 1-4 - 2015
- [c54]Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne:
Processing active devices on Si interposer and impact on cost. 3DIC 2015: TS11.2.1-TS11.2.4 - [c53]A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil:
Through silicon via to FinFET noise coupling in 3-D integrated circuits. ICICDT 2015: 1-4 - [c52]Herman Oprins, Vladimir Cherman, Geert Van der Plas, F. L. T. Maggioni, Joeri De Vos, Eric Beyne:
Thermal experimental and modeling analysis of high power 3D packages. ICICDT 2015: 1-4 - [c51]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean:
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2014
- [j36]Bart Vandevelde, Andrej Ivankovic, B. Debecker, Melina Lofrano, Kris Vanstreels, Wei Guo, Vladimir Cherman, Marcel Gonzalez, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Zsolt Tokei:
Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. Microelectron. Reliab. 54(6-7): 1200-1205 (2014) - [c50]X. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne:
Analysis of 3D interconnect performance: Effect of the Si substrate resistivity. 3DIC 2014: 1-4 - [c49]Joeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne:
Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. 3DIC 2014: 1-7 - 2013
- [c48]Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne:
Design issues in heterogeneous 3D/2.5D integration. ASP-DAC 2013: 403-410 - [c47]Michael H. Perrott, Geert Van der Plas:
Session 15 overview: Data converter techniques. ISSCC 2013: 266-267 - 2012
- [j35]Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47(4): 990-1002 (2012) - [j34]Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas:
A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 80-92 (2012) - [c46]Wei Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, Mario Gonzalez, Yann Civale, Augusto Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, Kenneth J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne, Bart Swinnen:
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. ICICDT 2012: 1-4 - 2011
- [j33]Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - [j32]Herman Oprins, Adi Srinivasan, Miroslav Cupák, Vladimir Cherman, Cristina Torregiani, Michele Stucchi, Geert Van der Plas, Paul Marchal, Bart Vandevelde, E. Cheng:
Fine grain thermal modeling and experimental validation of 3D-ICs. Microelectron. J. 42(4): 572-578 (2011) - [c45]Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne:
In-tier diagnosis of power domains in 3D TSV ICs. 3DIC 2011: 1-6 - [c44]Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, Wenqi Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte:
Analysis of microbump induced stress effects in 3D stacked IC technologies. 3DIC 2011: 1-5 - [c43]Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas:
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. CICC 2011: 1-4 - [c42]Eric Beyne, Pol Marchal, Geert Van der Plas:
3D heterogeneous system integration: application driver for 3D technology development. DAC 2011: 213 - [c41]Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas:
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. DATE 2011: 505-506 - [p1]Jan Craninckx, Geert Van der Plas:
Low-Power ADCs for Bio-Medical Applications. Bio-Medical CMOS ICs 2011: 157-190 - 2010
- [j31]Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx:
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. IEEE J. Solid State Circuits 45(6): 1159-1171 (2010) - [j30]Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert:
Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. IEEE J. Solid State Circuits 45(6): 1198-1208 (2010) - [j29]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 45(10): 2080-2090 (2010) - [j28]Stephane Bronckers, Geert Van der Plas, Gerd Vandersteen, Yves Rolain:
Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors. IEEE Trans. Instrum. Meas. 59(6): 1727-1733 (2010) - [c40]Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC 2010: 1-4 - [c39]Alonso Morgado, Rocío del Río, José M. de la Rosa, Lynn Bos, Julien Ryckaert, Geert Van der Plas:
A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. ESSCIRC 2010: 418-421 - [c38]Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal:
3D integration: Circuit design, test, and reliability challenges. IOLTS 2010: 217 - [c37]Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne:
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC 2010: 148-149 - [c36]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC 2010: 296-297
2000 – 2009
- 2009
- [j27]Sergio Saponara, Pierluigi Nuzzo, Claudio Nani, Geert Van der Plas, Luca Fanucci:
Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters. IEICE Trans. Electron. 92-C(6): 843-851 (2009) - [j26]Guy Torfs, Zhisheng Li, Johan Bauwelinck, Xin Yin, Jan Vandewege, Geert Van der Plas:
A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs. IEICE Trans. Electron. 92-C(10): 1328-1330 (2009) - [j25]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits 44(3): 874-882 (2009) - [j24]Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas:
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits 44(11): 2873-2880 (2009) - [j23]Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, Yves Rolain:
A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1613-1626 (2009) - [j22]Stephane Bronckers, Gerd Vandersteen, Ludwig De Locht, Michael Libois, Geert Van der Plas, Yves Rolain:
Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO. IEEE Trans. Instrum. Meas. 58(8): 2706-2713 (2009) - [c35]Panagiotis Asimakopoulos, Geert Van der Plas, Alexandre Yakovlev, Paul Marchal:
Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. 3DIC 2009: 1-5 - [c34]Dragomir Milojevic, Trevor E. Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, Paul Marchal:
Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. 3DIC 2009: 1-6 - [c33]Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx:
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. ESSCIRC 2009: 336-339 - [c32]Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas:
A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. ISSCC 2009: 176-177 - 2008
- [j21]Geert Van der Plas, Bob Verbruggen:
A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits 43(12): 2631-2640 (2008) - [j20]Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, Geert Van der Plas:
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1441-1454 (2008) - [c31]Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas:
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. DATE 2008: 1390-1393 - [c30]Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx:
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. ISSCC 2008: 238-239 - [c29]Geert Van der Plas, Bob Verbruggen:
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. ISSCC 2008: 242-243 - [c28]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. ISSCC 2008: 252-253 - [c27]Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak:
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. ISSCC 2008: 528-529 - 2007
- [j19]Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas:
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits 42(11): 2515-2527 (2007) - [j18]Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx:
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. IEEE J. Solid State Circuits 42(12): 2860-2869 (2007) - [j17]Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidyanathan Subramanian, Nadine Collaert, Malgorzata Jurczak, Stefaan Decoutere:
The Potential of FinFETs for Analog and RF Circuit Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2541-2551 (2007) - [c26]Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain:
Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. DATE 2007: 1520-1525 - [c25]Jonathan Borremans, Piet Wambacq, Geert Van der Plas, Yves Rolain, Maarten Kuijk:
A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS. ESSCIRC 2007: 376-379 - [c24]Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx:
A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. ESSCIRC 2007: 484-487 - [c23]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941 - [c22]Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx:
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. ISSCC 2007: 120-591 - [c21]Jan Craninckx, Geert Van der Plas:
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. ISSCC 2007: 246-600 - [i1]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. CoRR abs/0710.4723 (2007) - 2006
- [j16]Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke:
Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j15]Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk:
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits 41(9): 2040-2051 (2006) - [j14]Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1146-1154 (2006) - [j13]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 296-305 (2006) - [j12]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 23-33 (2006) - [c20]Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni:
A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. DAC 2006: 873-878 - [c19]Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx:
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC 2006: 368-377 - [c18]Geert Van der Plas, Stefaan Decoutere, Stéphane Donnay:
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process. ISSCC 2006: 2310- - 2005
- [j11]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Maarten Kuijk:
Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. IEEE J. Solid State Circuits 40(7): 1472-1481 (2005) - [j10]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 65-76 (2005) - [j9]Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx:
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2515-2525 (2005) - [c17]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Substrate noise immune design of an LC-tank VCO using sensitivity functions. CICC 2005: 477-480 - [c16]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE 2005: 270-275 - 2004
- [j8]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39(7): 1119-1130 (2004) - [j7]Jurgen Deveugele, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 191-195 (2004) - [c15]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC 2004: 501-504 - [c14]Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859 - [c13]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93 - [c12]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Performance degradation of an LC-tank VCO by impact of digital switching noise. ESSCIRC 2004: 119-122 - [c11]Tao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen:
A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL. ESSCIRC 2004: 167-170 - 2003
- [c10]Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC 2003: 257-260 - 2002
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