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Tung-Hua Yeh

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2010 – 2019

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2017
[c4]
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  dblp key:
  - conf/vlsi-dat/PursleyY17
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David Pursley, Tung-Hua Yeh:
High-level low-power system design optimization. VLSI-DAT 2017: 1-4
2014
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  - conf/socc/LaiHHLYCL14
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Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC 2014: 286-291
2012
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  - journals/tvlsi/YehW12
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Tung-Hua Yeh, Sying-Jyan Wang:
Power-Aware High-Level Synthesis With Clock Skew Management. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 167-171 (2012)
2010
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Tung-Hua Yeh, Sying-Jyan Wang:
Thermal Safe High Level Test Synthesis for Hierarchical Testability. Asian Test Symposium 2010: 337-342

2000 – 2009

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2009
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Sying-Jyan Wang, Tung-Hua Yeh:
High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1583-1596 (2009)
2007
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Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh:
Test Data Compression for Minimum Test Application Time. J. Inf. Sci. Eng. 23(6): 1901-1909 (2007)
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Sying-Jyan Wang, Tung-Hua Yeh:
High-level test synthesis for delay fault testability. DATE 2007: 45-50

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