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ORCIDMakoto Sugihara
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2010 – 2019
- 2014
[j14]Makoto Sugihara:
Minimization of the Fabrication Cost for a Bridged-Bus-Based TDMA System under Hard Real-Time Constraints. IEICE Trans. Inf. Syst. 97-D(12): 3041-3051 (2014)- 2013
- [j13]Makoto Sugihara, Akihito Iwanaga:
Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications. Inf. Media Technol. 8(1): 130-136 (2013) - [j12]Makoto Sugihara, Akihito Iwanaga:
Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints. Inf. Media Technol. 8(3): 637-645 (2013) - [j11]Makoto Sugihara, Akihito Iwanaga:
Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications. J. Inf. Process. 21(1): 46-52 (2013) - [j10]Makoto Sugihara, Akihito Iwanaga:
Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints. J. Inf. Process. 21(3): 563-571 (2013) - 2011
- [j9]Makoto Sugihara:
A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors. IEICE Trans. Electron. 94-C(4): 477-486 (2011) - 2010
- [j8]Makoto Sugihara:
Character-Size Optimization for Reducing the Number of EB Shots of MCC Lithographic Systems. IEICE Trans. Electron. 93-C(5): 631-639 (2010) - [j7]Makoto Sugihara:
On Synthesizing a Reliable Multiprocessor for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2560-2569 (2010) - [c12]Makoto Sugihara:
Dynamic Control Flow Checking Technique for Reliable Microprocessors. DSD 2010: 232-239
2000 – 2009
- 2009
- [j6]Makoto Sugihara:
Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1121-1128 (2009) - [c11]Makoto Sugihara:
Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints. DSD 2009: 333-340 - 2008
- [j5]Makoto Sugihara, Tohru Ishihara
, Kazuaki J. Murakami:
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Trans. Electron. 91-C(4): 410-417 (2008) - [j4]Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami:
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3451-3460 (2008) - [c10]Makoto Sugihara:
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. ISQED 2008: 757-762 - 2007
- [j3]Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami:
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Trans. Electron. 90-C(5): 1012-1020 (2007) - [j2]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Trans. Electron. 90-C(10): 1983-1991 (2007) - [c9]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495 - 2006
- [j1]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. 89-C(3): 377-383 (2006) - [c8]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006 - [c7]Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto:
A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED 2006: 196-203 - 2005
- [c6]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC 2005: 137-140 - 2004
- [c5]Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga:
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186 - 2002
- [c4]Makoto Sugihara, Hiroto Yasuura:
Optimization of Test Accesses with a Combined BIST and External Test Scheme. ASP-DAC/VLSI Design 2002: 683-688 - 2000
- [c3]Makoto Sugihara, Hiroto Yasuura, Hiroshi Date:
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE 2000: 134-140 - [c2]Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara:
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. PDPTA 2000
1990 – 1999
- 1998
- [c1]Makoto Sugihara, Hiroshi Date, Hiroto Yasuura:
A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC 1998: 465-472
Coauthor Index
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