Google
Google Scholar
Semantic Scholar
MS Academic
CiteSeerX
ORCIDLei He 0001
Person information
- affiliation: University of California, Los Angeles, Department of Electrical Engineering, CA, USA
- affiliation (1999 - 2002): University of Wisconsin, Madison, WI, USA
Other persons with the same name
- Lei He — disambiguation page
- Lei He 0002
![[0000-0002-7433-499X]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7433-499X")
— Hefei University of Technology, School of Computer and Information, China - Lei He 0003 — Central South University, School of Business, Changsha, China
- Lei He 0004 — Chinese Academy of Sciences, National Laboratory of Pattern Recognition, Beijing, China
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2020
[j70]Sai Xu, Shuai Han, Weixiao Meng, Lei He:
QoS-Based Robust Cooperative-Jamming-Aided Beamforming for Correlated Wiretap Channels. IEEE Signal Process. Lett. 27: 216-220 (2020)- [j69]Yunxuan Yu, Chen Wu, Tiandong Zhao, Kun Wang, Lei He:
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 35-47 (2020) - [j68]Yunxuan Yu, Tiandong Zhao, Mingyu Wang, Kun Wang, Lei He:
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1545-1556 (2020) - [j67]Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He:
Correlation-Based Cooperative Jamming to Enhance Secrecy With Receiver-Side Correlation. IEEE Trans. Veh. Technol. 69(2): 1903-1912 (2020) - [j66]Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He:
Correlation-Based Secure Transmission for Correlated MISO Wiretap Channels. IEEE Wirel. Commun. Lett. 9(3): 302-305 (2020) - [j65]Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He:
Robust Beamforming Design for Correlated MISO Wiretap Channels Under Channel Uncertainty. IEEE Wirel. Commun. Lett. 9(4): 553-557 (2020) - [c117]Yunxuan Yu, Tiandong Zhao, Kun Wang, Lei He:
Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks. FPGA 2020: 122-132
2010 – 2019
- 2016
- [c116]Yunxuan Yu, Lei He:
FPGA Power Estimation Using Automatic Feature Selection (Abstract Only). FPGA 2016: 282 - 2014
- [j64]Fang Gong, Hao Yu, Yiyu Shi, Lei He:
Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges. IEEE Des. Test 31(4): 6-15 (2014) - [j63]Lerong Cheng, Wenyao Xu, Fengbo Ren, Fang Gong, Puneet Gupta, Lei He:
Statistical timing and power analysis of VLSI considering non-linear dependence. Integr. 47(4): 487-498 (2014) - [j62]Zhe Feng, Naifeng Jing, Lei He:
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2225-2228 (2014) - [c115]Wei Wu, Fang Gong, GengSheng Chen, Lei He:
A fast and provably bounded failure analysis of memory circuits in high dimensions. ASP-DAC 2014: 424-429 - [c114]Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He:
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. DAC 2014: 82:1-82:6 - 2013
- [j61]Wei Wu, Fang Gong, Rahul Krishnan, Lei He, Hao Yu:
Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms. IEEE Des. Test 30(1): 26-35 (2013) - [j60]Chaofan Yu, Lingli Wang, Chun Zhang, Yu Hu, Lei He:
Fast Filter-Based Boolean Matchers. IEEE Embed. Syst. Lett. 5(4): 65-68 (2013) - [j59]Sina Basir-Kazeruni, Hao Yu, Fang Gong, Yu Hu, Chunchen Liu, Lei He:
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. Integr. 46(1): 22-32 (2013) - [j58]Fang Gong, Sina Basir-Kazeruni, Lei He, Hao Yu:
Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 24-33 (2013) - [j57]Wei Yao, Siming Pan, Brice Achkir, Jun Fan, Lei He:
Modeling and Application of Multi-Port TSV Networks in 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 487-496 (2013) - [c113]Ming-Chun Huang, Wenyao Xu, Jason J. Liu, Yi Su, Lei He, Majid Sarrafzadeh:
Inconspicuous Personal Computer Protection with Touch-Mouse. HCI (27) 2013: 29-38 - [c112]Rahul Krishnan, Wei Wu, Fang Gong, Lei He:
Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy. ISQED 2013: 572-579 - 2012
- [j56]Fang Gong, Wenyao Xu, Jueh-Yu Lee, Lei He, Majid Sarrafzadeh:
NeuroGlasses: A Neural Sensing Healthcare System for 3-D Vision Technology. IEEE Trans. Inf. Technol. Biomed. 16(2): 198-204 (2012) - [j55]Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He:
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. ACM Trans. Design Autom. Electr. Syst. 17(1): 10:1-10:23 (2012) - [j54]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He:
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18(1): 13:1-13:18 (2012) - [j53]Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He:
Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 5(2): 9:1-9:19 (2012) - [j52]Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 89-97 (2012) - [j51]Lerong Cheng, Fang Gong, Wenyao Xu, Jinjun Xiong, Lei He, Majid Sarrafzadeh:
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1383-1391 (2012) - [j50]Fang Gong, Hao Yu, Lingli Wang, Lei He:
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1729-1737 (2012) - [c111]Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He:
A fast estimation of SRAM failure rate using probability collectives. ISPD 2012: 41-48 - [c110]Wenyao Xu, Ming-Chun Huang, Navid Amini, Jason J. Liu, Lei He, Majid Sarrafzadeh:
Smart insole: a wearable system for gait analysis. PETRA 2012: 18 - 2011
- [j49]Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao:
System-in-Package: Electrical and Layout Perspectives. Found. Trends Electron. Des. Autom. 4(4): 223-306 (2011) - [j48]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 388-401 (2011) - [j47]Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh:
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1372-1381 (2011) - [j46]Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 508-512 (2011) - [c109]Fang Gong, Hao Yu, Lei He:
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials. DAC 2011: 298-303 - [c108]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL 2011: 282-285 - [c107]Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He:
Acceleration of Multi-agent Simulation on FPGAs. FPL 2011: 470-473 - [c106]Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He:
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. FPL 2011: 482-485 - [c105]Fang Gong, Hao Yu, Lei He:
Stochastic analog circuit behavior modeling by point estimation method. ISPD 2011: 175-182 - 2010
- [j45]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Accelerating Boolean Matching Using Bloom Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(10): 1775-1781 (2010) - [j44]Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010) - [j43]Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar:
Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 681-690 (2010) - [j42]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. 15(3): 27:1-27:21 (2010) - [j41]Yiyu Shi, Lei He:
EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 108-118 (2010) - [j40]Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He, Sheldon X.-D. Tan:
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1399-1411 (2010) - [c104]Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li:
Fault-tolerant resynthesis with dual-output LUTs. ASP-DAC 2010: 325-330 - [c103]Lerong Cheng, Puneet Gupta, Lei He:
On confidence in characterization and application of variation models. ASP-DAC 2010: 751-756 - [c102]Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He:
QuickYield: an efficient global-search based parametric yield estimation with performance constraints. DAC 2010: 392-397 - [c101]Manu Jose, Yu Hu, Rupak Majumdar, Lei He:
Rewiring for robustness. DAC 2010: 469-474 - [c100]Bingjun Xiao, Yiyu Shi, Lei He:
A universal state-of-charge algorithm for batteries. DAC 2010: 687-692 - [c99]Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. DATE 2010: 783-788 - [c98]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Building a faster boolean matcher using bloom filter. FPGA 2010: 185-188 - [c97]Ju-Yueh Lee, Zhe Feng, Lei He:
In-place decomposition for robustness in FPGA. ICCAD 2010: 143-148 - [c96]Yiyu Shi, Lei He:
Modeling and design for beyond-the-die power integrity. ICCAD 2010: 411-416 - [c95]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Engineering a scalable Boolean matching based on EDA SaaS 2.0. ICCAD 2010: 750-755
2000 – 2009
- 2009
- [j39]Hao Yu, Lei He, Mau-Chung Frank Chang:
Robust On-Chip Signaling by Staggered and Twisted Bundle. IEEE Des. Test Comput. 26(5): 92-104 (2009) - [j38]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 130-140 (2009) - [j37]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 207-216 (2009) - [j36]Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 591-595 (2009) - [j35]Lerong Cheng, Puneet Gupta, Lei He:
Efficient Additive Statistical Leakage Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1777-1781 (2009) - [j34]Hao Yu, Joanna Ho, Lei He:
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Trans. Design Autom. Electr. Syst. 14(3): 41:1-41:31 (2009) - [c94]Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He:
Incremental and on-demand random walk for iterative power distribution network analysis. ASP-DAC 2009: 185-190 - [c93]Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. ASP-DAC 2009: 373-378 - [c92]Lerong Cheng, Puneet Gupta, Lei He:
Accounting for non-linear dependence using function driven component analysis. ASP-DAC 2009: 474-479 - [c91]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109 - [c90]Fang Gong, Hao Yu, Lei He:
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. DAC 2009: 764-769 - [c89]Zhe Feng, Yu Hu, Lei He, Rupak Majumdar:
IPR: In-Place Reconfiguration for FPGA fault tolerance. ICCAD 2009: 105-108 - [c88]Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Joint design-time and post-silicon optimization for digitally tuned analog circuits. ICCAD 2009: 725-730 - [c87]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Diffusion-driven congestion reduction for substrate topological routing. ISPD 2009: 175-180 - [c86]Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu:
Worst case timing jitter and amplitude noise in differential signaling. ISQED 2009: 40-46 - [c85]Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. ISQED 2009: 702-707 - 2008
- [j33]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 726-737 (2008) - [j32]Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1253-1263 (2008) - [j31]King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1498-1502 (2008) - [j30]Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1751-1760 (2008) - [j29]Yu Hu, Yan Lin, Lei He, Tim Tuan:
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13(2): 30:1-30:29 (2008) - [j28]Yan Lin, Lei He, Mike Hutton:
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 124-133 (2008) - [j27]Hao Yu, Yiyu Shi, Lei He, Tanay Karnik:
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1609-1619 (2008) - [c84]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian statistical timing analysis using second-order polynomial fitting. ASP-DAC 2008: 298-303 - [c83]Yiyu Shi, Lei He, C.-J. Richard Shi:
Scalable Symbolic Model Order Reduction. BMAS 2008: 112-117 - [c82]Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
FPGA area reduction by multi-output function based sequential resynthesis. DAC 2008: 24-29 - [c81]Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar:
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. DAC 2008: 179-184 - [c80]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Topological routing to maximize routability for package substrate. DAC 2008: 566-569 - [c79]Lerong Cheng, Yan Lin, Lei He:
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA 2008: 159-168 - [c78]Yu Hu, Zhe Feng, Lei He, Rupak Majumdar:
Robust FPGA resynthesis based on fault-tolerant Boolean matching. ICCAD 2008: 706-713 - 2007
- [j26]Yan Lin, Mike Hutton, Lei He:
Statistical placement for FPGAs considering. IET Comput. Digit. Tech. 1(4): 267-275 (2007) - [j25]Jinjun Xiong, Lei He:
Full-chip multilevel routing for power and signal integrity. Integr. 40(3): 226-234 (2007) - [j24]Jinjun Xiong, Vladimir Zolotov, Lei He:
Robust Extraction of Spatial Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 619-631 (2007) - [j23]Jun Chen, Lei He:
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 734-738 (2007) - [j22]Jinjun Xiong, Lei He:
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 739-742 (2007) - [j21]Fei Li, Yan Lin, Lei He:
Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 752-764 (2007) - [j20]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 845-857 (2007) - [j19]Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1211-1221 (2007) - [j18]Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit-simulated obstacle-aware Steiner routing. ACM Trans. Design Autom. Electr. Syst. 12(3): 28:1-28:18 (2007) - [j17]Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He:
Microarchitecture Configurations and Floorplanning Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 830-841 (2007) - [c77]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 - [c76]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. DAC 2007: 250-255 - [c75]Hao Yu, Chunta Chu, Lei He:
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. DAC 2007: 618-621 - [c74]Yan Lin, Lei He:
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE 2007: 636-641 - [c73]Yan Lin, Lei He:
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA 2007: 80-88 - [c72]Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. ICCAD 2007: 188-193 - [c71]Yan Lin, Lei He:
Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD 2007: 194-198 - [c70]Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. ICCAD 2007: 350-353 - [c69]Chunta Chu, Xinyi Zhang, Lei He, Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load. ICCAD 2007: 586-589 - [c68]Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient decoupling capacitance budgeting considering operation and process variations. ICCAD 2007: 803-810 - [c67]Yiyu Shi, Lei He:
Empire: an efficient and compact multiple-parameterized model order reduction method. ISPD 2007: 51-58 - [c66]Hao Yu, Yu Hu, Chunchen Liu, Lei He:
Minimal skew clock embedding considering time variant temperature gradient. ISPD 2007: 173-180 - [c65]Yu Hu, King Ho Tam, Tong Jing, Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP 2007: 95-102 - 2006
- [j16]Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He:
Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1496-1509 (2006) - [j15]Jun Chen, Lei He:
Modeling and synthesis of multiport transmission line for multichannel communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1664-1676 (2006) - [j14]Yan Lin, Lei He:
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2023-2034 (2006) - [c64]Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He:
Constraint driven I/O planning and placement for chip-package co-design. ASP-DAC 2006: 207-212 - [c63]Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC 2006: 630-635 - [c62]Hao Yu, Yiyu Shi, Lei He:
Fast analysis of structured power grid by triangularization based structure preserving model order reduction. DAC 2006: 205-210 - [c61]Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit simulation based obstacle-aware Steiner routing. DAC 2006: 385-388 - [c60]Yu Hu, Yan Lin, Lei He, Tim Tuan:
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC 2006: 478-483 - [c59]Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton:
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL 2006: 1-6 - [c58]Mike Hutton, Yan Lin, Lei He:
Placement and Timing for FPGAs Considering Variations. FPL 2006: 1-7 - [c57]Hao Yu, Yiyu Shi, Lei He, David Smart:
A fast block structure preserving model order reduction for inverse inductance circuits. ICCAD 2006: 7-12 - [c56]Hao Yu, Joanna Ho, Lei He:
Simultaneous power and thermal integrity driven via stapling in 3D ICs. ICCAD 2006: 802-808 - [c55]Hao Yu, Yiyu Shi, Lei He, Tanay Karnik:
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. ISLPED 2006: 156-161 - [c54]Yan Lin, Yu Hu, Lei He, Vijay Raghunat:
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED