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Shuilong Huang
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2020 – today
- 2023
- [j3]Zheng Li
, Yating Yang
, Mingyang Liu, Wei Liu, Ying Hou
, Zihui Wei, Xiaosong Wang, Zhenming Li, Shuilong Huang, Yu Liu
:
A 16.5-μW 73.7-dB-SNDR Second-Order Fully Passive Noise-Shaping SAR ADC With a Hybrid Switching Procedure. IEEE Access 11: 89298-89308 (2023)
2010 – 2019
- 2017
- [j2]Zihui Wei, Yanbin Xiao, Shuilong Huang:
11b 60 MHz pipelined ADC with inverter-based class AB amplifier in 28 nm CMOS technology. IEICE Electron. Express 14(5): 20170047 (2017)
2000 – 2009
- 2008
- [j1]Shuilong Huang, Zhihua Wang:
System Design Considerations of Highly-Integrated SigmaDelta fractional-n Frequency synthesizer. J. Circuits Syst. Comput. 17(2): 169-181 (2008) - 2007
- [c3]Shuilong Huang, Huainan Ma, Zhihua Wang:
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. DATE 2007: 291-296 - [c2]Shuilong Huang, Zhihua Wang:
A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm. ISCAS 2007: 3924-3927 - 2006
- [c1]Shuilong Huang, Zhihua Wang, Huainan Ma:
A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm. APCCAS 2006: 203-206
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