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ORCIDShekhar Y. Borkar
Shekhar Borkar
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- affiliation: Intel
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2010 – 2019
- 2017
[j22]Vincent Cavé, Romain Cledat, Paul Griffin, Ankit More, Bala Seshasayee, Shekhar Borkar, Sanjay Chatterjee, Dave Dunning, Joshua B. Fryman:
Traleika Glacier: A hardware-software co-designed approach to exascale computing. Parallel Comput. 64: 33-49 (2017)- 2016
- [p2]Shekhar Borkar:
Extreme Energy Efficiency by Near Threshold Voltage Operation. Near Threshold Computing 2016: 3-18 - 2015
- [j21]Gregory K. Chen, Mark Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Y. Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(1): 59-67 (2015) - 2014
- [c64]Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. ASP-DAC 2014: 388-389 - [c63]Robert Pawlowski, Joseph Crop, Minki Cho, James W. Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Y. Borkar, Patrick Yin Chiang:
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. CICC 2014: 1-4 - [c62]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Y. Borkar, Vivek De:
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC 2014: 276-277 - 2013
- [j20]Shekhar Borkar:
Centip3De demonstrates more than Moore...: technical perspective. Commun. ACM 56(11): 96 (2013) - [j19]Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits 48(1): 128-139 (2013) - [c61]Tanay Karnik, Mondira (Mandy) Pant, Shekhar Borkar:
Power management and delivery for high-performance microprocessors. DAC 2013: 159:1-159:3 - [c60]Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu:
Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA 2013: 198-209 - [c59]Shekhar Borkar:
Exascale Computing - A Fact or a Fiction? IPDPS 2013: 3 - [c58]Shekhar Borkar, Uming Ko, Ali Keshavarzi, Eugenio Cantatore:
EP3: Empowering the killer SoC applications of 2020. ISSCC 2013: 517 - 2012
- [c57]Himanshu Kaul, Mark Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
Near-threshold voltage (NTV) design: opportunities and challenges. DAC 2012: 1153-1158 - [c56]Richard F. Barrett, Shekhar Borkar, Sudip S. Dosanjh, Simon D. Hammond, Michael A. Heroux, Xiaobo Sharon Hu
, Justin Luitjens, Steven G. Parker, John Shalf, Li Tang:
On the Role of Co-design in High Performance Computing. High Performance Computing Workshop (2) 2012: 141-155 - [c55]Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar:
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC 2012: 66-68 - [c54]Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC 2012: 182-184 - [c53]Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC 2012: 184-186 - [c52]Masaitsu Nakajima, Shekhar Borkar:
Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee. ISSCC 2012: 306-307 - [c51]Steven Hsu, Amit Agarwal, Mark Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC 2012: 118-119 - 2011
- [j18]Shekhar Borkar, Andrew A. Chien:
The future of microprocessors. Commun. ACM 54(5): 67-77 (2011) - [j17]Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. 5(3): 205-212 (2011) - [j16]Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart:
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46(1): 173-183 (2011) - [j15]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46(1): 184-193 (2011) - [c50]Shekhar Borkar:
3D integration for energy efficient system design. DAC 2011: 214-219 - [c49]Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
3DICs for tera-scale computing: a case study. ISPD 2011: 77-78 - [p1]Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar:
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. Low Power Networks-on-Chip 2011: 3-20 - 2010
- [j14]Shekhar Y. Borkar:
Want to be a bug buster? Commun. ACM 53(2): 105 (2010) - [j13]Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits 45(1): 95-102 (2010) - [c48]Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson:
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC 2010: 108-109 - [c47]Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC 2010: 110-111 - [c46]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175 - [c45]Amit Agarwal, Sanu Mathew, Steven Hsu, Mark Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar:
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC 2010: 328-329 - [c44]Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva Narendra:
The semiconductor industry in 2025. ISSCC 2010: 534-535 - [c43]Shekhar Y. Borkar:
Future of interconnect fabric: a contrarian view. SLIP 2010: 1-2
2000 – 2009
- 2009
- [j12]Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits 44(1): 107-114 (2009) - [j11]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - [c42]Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 - [c41]Shekhar Borkar:
Design perspectives on 22nm CMOS and beyond. DAC 2009: 93-94 - [c40]Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC 2009: 260-261 - 2008
- [j10]David Yeh, Li-Shiuan Peh, Shekhar Borkar, John A. Darringer, Anant Agarwal, Wen-mei W. Hwu:
Thousand-Core Chips [Roundtable]. IEEE Des. Test Comput. 25(3): 272-278 (2008) - [j9]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Hoskote, Nitin Borkar, Shekhar Borkar:
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits 43(1): 29-41 (2008) - [j8]Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar:
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits 43(1): 214-222 (2008) - [c39]Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye:
Custom is from Venus and synthesis from Mars. DAC 2008: 992 - [c38]Mark Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar:
A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. ESSCIRC 2008: 182-185 - [c37]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - [c36]Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC 2008: 316-317 - 2007
- [j7]Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar:
A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro 27(5): 51-61 (2007) - [c35]Shekhar Borkar:
Thousand Core ChipsA Technology Perspective. DAC 2007: 746-749 - [c34]Shekhar Borkar, Norman P. Jouppi, Per Stenström:
Microprocessors in the era of terascale integration. DATE 2007: 237-242 - [c33]Shekhar Borkar, William J. Dally:
Future of on-chip interconnection architectures. ISLPED 2007: 122 - [c32]Mark Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC 2007: 256-600 - 2006
- [j6]Shekhar Borkar:
Tackling variability and reliability challenges. IEEE Des. Test Comput. 23(6): 520 (2006) - [j5]Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 646-649 (2006) - [c31]Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini:
Tomorrow's analog: just dead or just different? DAC 2006: 709-710 - [c30]Shekhar Borkar:
Electronics beyond nano-scale CMOS. DAC 2006: 807-808 - [c29]Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu K. Mathew, R. Krishnamurthy, Shekhar Y. Borkar:
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC 2006: 1785-1797 - [c28]Shekhar Borkar:
Introduction to panel discussion Probabilistic & statistical design - the wave of the future. VLSI-SoC 2006 - [c27]Shekhar Borkar:
Probabilistic amp; Statistical Design - the Wave of the Future. VLSI-SoC (Selected Papers) 2006: 69-79 - 2005
- [j4]Shekhar Y. Borkar:
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro 25(6): 10-16 (2005) - [c26]Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105 - [c25]Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106 - [c24]Shekhar Y. Borkar:
VLSI Design Challenges for Gigascale Integration. VLSI Design 2005: 27 - 2004
- [c23]Shekhar Borkar, Tanay Karnik, Vivek De:
Design and reliability challenges in nanometer technologies. DAC 2004: 75 - [c22]Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah:
Is statistical timing statistically significant? DAC 2004: 498 - [c21]Shekhar Y. Borkar:
Microarchitecture and Design Challenges for Gigascale Integration. MICRO 2004: 3 - 2003
- [j3]Shekhar Borkar:
Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law. ACM Queue 1(7): 26-33 (2003) - [c20]Shekhar Borkar, Tanay Karnik, Siva Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De:
Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 - [c19]Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf:
Nanometer design: place your bets. DAC 2003: 546-547 - [c18]Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED 2003: 122-127 - [c17]Shekhar Borkar:
Exponential Challenges, Exponential Rewards - The future of Moore's Law. VLSI-SOC 2003: 2 - 2002
- [j2]Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De:
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 91-95 (2002) - [c16]George Sery, Shekhar Borkar, Vivek De:
Life is CMOS: why chase the life after? DAC 2002: 78-83 - [c15]Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 - [c14]Tanay Karnik, Shekhar Borkar, Vivek De:
Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206 - [c13]Siva Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha Chandrakasan:
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED 2002: 19-23 - 2001
- [c12]Shekhar Borkar:
Low power design challenges for the decade (invited talk). ASP-DAC 2001: 293-296 - [c11]Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang:
Panel: Is Nanometer Design Under Control? DAC 2001: 591-592 - [c10]Ram Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar:
Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI 2001: 43-44 - [c9]Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar:
A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED 2001: 68-71 - [c8]James W. Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 - [c7]Siva Narendra, Vivek De, Dimitri A. Antoniadis, Anantha Chandrakasan, Shekhar Borkar:
Scaling of stack effect and its application for leakage reduction. ISLPED 2001: 195-200 - [c6]Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De:
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED 2001: 207-212 - 2000
- [c5]Vivek De, Shekhar Borkar:
Low power and high performance design challenges in future technologies. ACM Great Lakes Symposium on VLSI 2000: 1-6
1990 – 1999
- 1999
- [j1]Shekhar Borkar:
Design challenges of technology scaling. IEEE Micro 19(4): 23-29 (1999) - [c4]Vivek De, Shekhar Borkar:
Technology and design challenges for low power and high performance. ISLPED 1999: 163-168 - [c3]Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De:
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254 - 1990
- [c2]Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb:
Supporting Systolic and Memory Communciation in iWarp. ISCA 1990: 70-81
1980 – 1989
- 1988
- [c1]Shekhar Borkar, Robert Cohn, George W. Cox, Sha Gleason, Thomas R. Gross:
Warp: an integrated solution of high-speed parallel computing. SC 1988: 330-339
Coauthor Index
Mark Anders
aka: Mark A. Anders
aka: Mark A. Anders
Vivek De
aka: Vivek K. De
aka: Vivek K. De
Steven Hsu
aka: Steven K. Hsu
aka: Steven K. Hsu
Ram Krishnamurthy
aka: Ram K. Krishnamurthy
aka: Ram K. Krishnamurthy
Sanu Mathew
aka: Sanu K. Mathew
aka: Sanu K. Mathew
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