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ORCIDAvinoam Kolodny
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- affiliation: Technion - Israel Institute of Technology, Haifa, Israel
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2010 – 2019
- 2019
[j49]Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
:
Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud. IEEE J. Sel. Areas Commun. 37(5): 1072-1084 (2019)- 2017
- [j48]Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser:
Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. 16(1): 68-71 (2017) - 2016
- [j47]Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. J. Parallel Distributed Comput. 95: 3-14 (2016) - [j46]Ran Manevich, Israel Cidon, Avinoam Kolodny:
Design and dynamic management of hierarchical NoCs. Microprocess. Microsystems 40: 154-166 (2016) - [c52]Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy:
Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud. ANCS 2016: 87-98 - 2015
- [j45]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48: 116-128 (2015) - [j44]Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny:
Average latency and link utilization analysis of heterogeneous wormhole NoCs. Integr. 51: 92-106 (2015) - [j43]Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny:
VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 786-790 (2015) - [j42]Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky:
Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. IEEE Trans. Neural Networks Learn. Syst. 26(10): 2408-2421 (2015) - [j41]Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny, Michael Shabun, Nir Shmuel:
Heterogeneous NoC Router Architecture. IEEE Trans. Parallel Distributed Syst. 26(9): 2479-2492 (2015) - [j40]Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny:
Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1750-1759 (2015) - [i1]Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy:
Links as a Service (LaaS): Feeling Alone in the Shared Cloud. CoRR abs/1509.07395 (2015) - 2014
- [j39]Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13(1): 41-44 (2014) - [j38]Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny:
Distributed Adaptive Routing Convergence to Non-Blocking DCN Routing Assignments. IEEE J. Sel. Areas Commun. 32(1): 88-101 (2014) - [j37]Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny:
Designing single-cycle long links in hierarchical NoCs. Microprocess. Microsystems 38(8): 814-825 (2014) - [j36]Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky:
Logic operations in memory using a memristive Akers array. Microelectron. J. 45(11): 1429-1437 (2014) - [j35]Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 895-899 (2014) - [j34]Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2054-2066 (2014) - [c51]Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny:
Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing. Hot Interconnects 2014: 41-48 - 2013
- [j33]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. 46(4): 382-391 (2013) - [j32]Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 211-221 (2013) - [j31]Eitan Zahavi, Israel Cidon, Avinoam Kolodny:
Gana: A novel low-cost conflict-free NoC architecture. ACM Trans. Embed. Comput. Syst. 12(4): 109:1-109:20 (2013) - [c50]Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny:
Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip. DSD 2013: 769-776 - [c49]Ran Manevich, Israel Cidon, Avinoam Kolodny:
Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs). NOCS 2013: 1-8 - [c48]Shani Rehana, Or Turgeman, Ran Manevich, Avinoam Kolodny:
ViLoCoN - An ultra-lightweight lossless VLSI video codec. SoCC 2013: 172-177 - 2012
- [j30]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23(2): 292-300 (2012) - [j29]Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser:
Task Scheduling Based On Thread Essence and Resource Limitations. J. Comput. 7(1): 53-64 (2012) - [j28]Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny:
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. Microelectron. J. 43(4): 235-243 (2012) - [j27]Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson:
Exploring the limits of GPGPU scheduling in control flow bound applications. ACM Trans. Archit. Code Optim. 8(4): 29:1-29:22 (2012) - [c47]Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny:
Distributed adaptive routing for big-data applications running on data center networks. ANCS 2012: 99-110 - [c46]Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Energy metrics for power efficient crosslink and mesh topologies. ISCAS 2012: 1656-1659 - [c45]Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny:
HNOCS: Modular open-source simulator for Heterogeneous NoCs. ICSAMOS 2012: 51-57 - [c44]Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny:
Optimizing heterogeneous NoC design. SLIP 2012: 32-39 - [c43]Ran Manevich, Israel Cidon, Avinoam Kolodny:
Handling global traffic in future CMP NoCs. SLIP 2012: 40-47 - 2011
- [j26]Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez:
Static timing analysis for modeling QoS in networks-on-chip. J. Parallel Distributed Comput. 71(5): 687-699 (2011) - [j25]Yoni Aizik, Avinoam Kolodny:
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints. VLSI Design 2011: 845957:1-845957:13 (2011) - [c42]Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer:
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD 2011: 39-46 - [c41]Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman:
Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147 - [c40]Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny:
An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS 2011: 2593-2596 - [c39]Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny:
Delay analysis of wormhole based heterogeneous NoC. NOCS 2011: 161-168 - [c38]Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny:
NoCs simulation framework for OMNeT++. NOCS 2011: 265-266 - [p1]Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study. Low Power Networks-on-Chip 2011: 175-195 - 2010
- [j24]Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter:
Centralized Adaptive Routing for NoCs. IEEE Comput. Archit. Lett. 9(2): 57-60 (2010) - [j23]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1650-1654 (2010) - [j22]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 689-696 (2010) - [j21]Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar:
Asynchronous Current Mode Serial Communication. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1107-1117 (2010) - [j20]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1262 (2010) - [c37]Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny:
The Devolution of Synchronizers. ASYNC 2010: 94-103 - [c36]Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. DATE 2010: 1408-1413 - [c35]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20 - [c34]Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny:
Performance and Power Aware CMP Thread Allocation Modeling. HiPEAC 2010: 232-246 - [c33]Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Threads vs. caches: Modeling the behavior of parallel workloads. ICCD 2010: 274-281 - [c32]Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson:
Efficiency optimization of integrated DC-DC buck converters. ICECS 2010: 1208-1211 - [c31]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD 2010: 153-160 - [c30]Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser:
Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. PAAP 2010: 65-72
2000 – 2009
- 2009
- [j19]Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. 8(1): 25-28 (2009) - [j18]Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny:
QNoC asynchronous router. Integr. 42(2): 103-115 (2009) - [j17]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14(4): 55:1-55:28 (2009) - [j16]Avinoam Kolodny, Li-Shiuan Peh:
Special Section on International Symposium on Networks-on-Chip (NOCS). IEEE Trans. Very Large Scale Integr. Syst. 17(3): 317-318 (2009) - [c29]Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290 - [c28]Isask'har Walter, Israel Cidon, Avinoam Kolodny, Daniel Sigalov:
The era of many-modules SoC: revisiting the NoC mapping problem. NoCArc@MICRO 2009: 43-48 - [c27]Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
The design of a latency constrained, power optimized NoC for a 4G SoC. NOCS 2009: 86 - [c26]Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter:
Packet-level static timing analysis for NoCs. NOCS 2009: 88 - [c25]Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
Best of both worlds: A bus enhanced NoC (BENoC). NOCS 2009: 173-182 - 2008
- [j15]Isask'har Walter, Israel Cidon, Avinoam Kolodny:
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP. IEEE Comput. Archit. Lett. 7(2): 61-64 (2008) - [j14]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
On optimal ordering of signals in parallel wire bundles. Integr. 41(2): 253-268 (2008) - [j13]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13(4): 65:1-65:17 (2008) - [j12]Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman:
Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 894-907 (2008) - [j11]Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 908-921 (2008) - [c24]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Timing optimization in logic with interconnect. SLIP 2008: 19-26 - [c23]Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar:
Parallel vs. serial on-chip communication. SLIP 2008: 43-50 - [c22]Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA 2008: 1-10 - 2007
- [j10]Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. 6(1): 21-24 (2007) - [j9]Michael Behar, Avi Mendelson, Avinoam Kolodny:
Trace cache sampling filter. ACM Trans. Comput. Syst. 25(1): 3 (2007) - [j8]Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007: 90941:1-90941:15 (2007) - [c21]Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny:
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14 - [c20]Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947 - [c19]Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126 - [c18]Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148 - [c17]Avinoam Kolodny:
Networks on chips: keeping up with Rent's rule and Moore's law. SLIP 2007: 55-56 - 2006
- [j7]Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny:
Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1089-1100 (2006) - [j6]Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1276-1281 (2006) - [c16]Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny:
Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127 - [c15]Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14 - [c14]Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu:
Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI 2006: 173-179 - [c13]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS 2006 - [c12]Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman:
On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS 2006 - 2005
- [j5]Noam Dolev, Avner Kornfeld, Avinoam Kolodny:
Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology. J. Circuits Syst. Comput. 14(3): 515-532 (2005) - [c11]Michael Behar, Avi Mendelson, Avinoam Kolodny:
Trace Cache Sampling Filter. IEEE PACT 2005: 255-266 - [c10]Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 2-7 - [c9]Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603 - 2004
- [j4]Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Cost considerations in network on chip. Integr. 38(1): 19-42 (2004) - [j3]Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50(2-3): 105-128 (2004) - [c8]Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny:
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. ICECS 2004: 125-128 - [c7]Anastasia Barger, David Goren, Avinoam Kolodny:
Design and modelling of network on chip interconnects using transmission lines. ICECS 2004: 403-406 - [c6]Shay Michaely, Shmuel Wimer, Avinoam Kolodny:
Optimal resizing of bus wires in layout migration. ICECS 2004: 411-414 - [c5]Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Automatic hardware-efficient SoC integration by QoS network on chip. ICECS 2004: 479-482 - [c4]Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Micro-modem - reliability solution for NoC communications. ICECS 2004: 483-486 - [c3]Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Comparative analysis of serial vs parallel links in NoC. SoC 2004: 185-188 - [c2]Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir:
Interconnect-power dissipation in a microprocessor. SLIP 2004: 7-13 - 2003
- [j2]Y. Elboim, Avinoam Kolodny, Ran Ginosar:
A clock-tuning circuit for system-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 616-626 (2003) - [j1]O. Milter, Avinoam Kolodny:
Crosstalk noise reduction in synthesized digital logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1153-1158 (2003) - [c1]Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC 2003: 99-104
Coauthor Index
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