• 
  Tohru Furuyama: Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible? 1
• 
  Alan Naumann: Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law? 2

Design records

• 
  Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun: ATLAS: a chip-multiprocessor with transactional memory support. 3-8
• 
  Fabio Campi, Antonio Deledda, Matteo Pizzotti, Luca Ciccarelli, Pier Luigi Rolandi, Claudio Mucci, Andrea Lodi, Arseni Vitkovski, Luca Vanzolini: A dynamically adaptive DSP for heterogeneous reconfigurable platforms. 9-14
• 
  Phillip Stanley-Marbell, Diana Marculescu: An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface. 15-20
• 
  Zhuan Ye, John Grosspietsch, Gokhan Memik: Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio. 21-26

Design for testability for SoCs

• 
  Ozgur Sinanoglu, Tsvetomir Petrov: A non-intrusive isolation approach for soft cores. 27-32
• 
  Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar: Unknown blocking scheme for low control data volume and high observability. 33-38
• 
  Quming Zhou, Kedarnath J. Balakrishnan: Test cost reduction for SoC using a combined approach to test data compression and test scheduling. 39-44
• 
  Sying-Jyan Wang, Tung-Hua Yeh: High-level test synthesis for delay fault testability. 45-50

Communication synthesis under timing constraints

• 
  Traian Pop, Paul Pop, Petru Eles, Zebo Peng: Bus access optimisation for FlexRay-based distributed embedded systems. 51-56
• 
  Nadathur Satish, Kaushik Ravindran, Kurt Keutzer: A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors. 57-62
• 
  Chuan Lin, Aiguo Xie, Hai Zhou: Design closure driven delay relaxation based on convex cost network flow. 63-68

Performance modelling and synthesis of analogue/mixed-signal circuits

• 
  Varun Aggarwal, Una-May O'Reilly: Simulation-based reusable posynomial models for MOS transistor parameters. 69-74
• 
  Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. 75-80
• 
  Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen: An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. 81-86
• 
  Ömer Yetik, Orkun Saglamdemir, Selçuk Talay, Günhan Dündar: Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB. 87-92

System level mapping and simulation

• 
  Wei Zheng, Marco Di Natale, Claudio Pinello, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli: Synthesis of task and message activation models in real-time distributed automotive systems. 93-98
• 
  Christopher Ostler, Karam S. Chatha: An ILP formulation for system-level application mapping on network processor architectures. 99-104
• 
  Paolo Destro, Franco Fummi, Graziano Pravadelli: A smooth refinement flow for co-designing HW and SW threads. 105-110
• 
  Youssef N. Naguib, Rafik S. Guindi: Speeding up SystemC simulation through process splitting. 111-116
• 
  Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal: Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. 117-122

Algorithms and applications of run-time reconfiguration

• 
  Florian Dittmann, Stefan Frank: Hard real-time reconfiguration port scheduling. 123-128
• 
  Jin Cui, Qingxu Deng, Xiuqiang He, Zonghua Gu: An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs. 129-134
• 
  Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. Shaheen: Improving utilization of reconfigurable resources using two dimensional compaction. 135-140
• 
  Roman L. Lysecky: Low-power warp processor for power efficient high-performance embedded systems. 141-146
• 
  Yang Qu, Juha-Pekka Soininen, Jari Nurmi: Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices. 147-152
• 
  Mona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem: Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver. 153-158

IP designs for media processing and other computational intensive kernels

• 
  Markos E. Papadonikolakis, Vasilleios Pantazis, Athanasios Kakarountas: Efficient high-performance ASIC implementation of JPEG-LS encoder. 159-164
• 
  Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan: Improve CAM power efficiency using decoupled match line scheme. 165-170
• 
  André B. J. Kokkeler, Gerard J. M. Smit, Thijs Krol, Jan Kuper: Cyclostationary feature detection on a tiled-SoC. 171-176
• 
  C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet: Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. 177-182
• 
  Esra Sahin, Ilker Hamzaoglu: Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. 183-188
• 
  Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno: Interactive presentation: An FPGA implementation of decision tree classification. 189-194
• 
  Nishant R. Srivastava: Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling. 195-200

Test infrastructure of SoCs and its verification

• 
  Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang: SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling. 201-206
• 
  Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: Optimized integration of test compression and sharing for SOC testing. 207-212
• 
  Oliver Spang, Hans Martin von Staudt, Michael G. Wahl: A sophisticated memory test engine for LCD display drivers. 213-218
• 
  Thuyen Le, Tilman Glökler, Jason Baumgartner: Formal verification of a pervasive interconnect bus system in a high-performance microprocessor. 219-224
• 
  Ehab Anis, Nicola Nicolici: Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. 225-230
• 
  Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara: Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. 231-236

Hot topic - Microprocessors in the era of terascale integration

• 
  Shekhar Borkar, Norman P. Jouppi, Per Stenström: Microprocessors in the era of terascale integration. 237-242

Statistical/nonlinear analysis and verification for analogue circuits

• 
  M. Zhang, Markus Olbrich, D. Seider, M. Frerichs, Harald Kinzelbach, Erich Barke: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. 243-248
• 
  Ghiath Al Sammane, Mohamed H. Zaki, Sofiène Tahar: A symbolic methodology for the verification of analog and mixed signal designs. 249-254
• 
  Dani Tannir, Roni Khazaka: Efficient nonlinear distortion analysis of RF circuits. 255-260
• 
  Jonathan Borremans, Ludwig De Locht, Piet Wambacq, Yves Rolain: Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis. 261-266
• 
  John Lataire, Gerd Vandersteen, Rik Pintelon: Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations. 267-272

System modeling and specification

• 
  Simon Schliecker, Steffen Stein, Rolf Ernst: Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis. 273-278
• 
  Hiren D. Patel, Sandeep K. Shukla: Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL. 279-284
• 
  Marc Geilen, Twan Basten: A calculator for Pareto points. 285-290
• 
  Shuilong Huang, Huainan Ma, Zhihua Wang: Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. 291-296
• 
  Fei Gong, Xiaobo Wu: Interactive presentation: System level power optimization of Sigma-Delta modulator. 297-300
• 
  Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner: Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. 301-306

Design space exploration and nano-technologies for reconfigurable computing

• 
  Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud: Assessing carbon nanotube bundle interconnect for future FPGA architectures. 307-312
• 
  Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid: Two-level microprocessor-accelerator partitioning. 313-318
• 
  Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Design space exploration of partially re-configurable embedded processors. 319-324
• 
  Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. 325-330

Implementation of LDPC codecs for various communication standards

• 
  Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci: Low complexity LDPC code decoders for next generation standards. 331-336
• 
  John Dielissen, Andries Hekstra: Non-fractional parallelism in LDPC decoder implementations. 337-342
• 
  Weihuang Wang, Gwan Choi: Minimum-energy LDPC decoder for real-time mobile application. 343-348
• 
  Zahid Khan, Tughrul Arslan: Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture. 349-354
• 
  Claudio Mucci, Luca Vanzolini, Fabio Campi, Mario Toma: Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture. 355-360

Testing NoCs

• 
  Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi: Using the inter- and intra-switch regularity in NoC switch testing. 361-366
• 
  Kim Petersén, Johnny Öberg: Toward a scalable test methodology for 2D-mesh Network-on-Chips. 367-372
• 
  Oussama Laouamri, Chouki Aktouf: Remote testing and diagnosis of System-on-Chips using network management frameworks. 373-378

Synthesis at system and architectural levels

• 
  Qubo Hu, Arnout Vandecappelle, Per Gunnar Kjeldsberg, Francky Catthoor, Martin Palkovic: Fast memory footprint estimation based on maximal dependency vector calculation. 379-384
• 
  Hongwei Zhu, Ilie I. Luican, Florin Balasa: Mapping multi-dimensional signals into hierarchical memory organizations. 385-390
• 
  Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda: The impact of loop unrolling on controller delay in high level synthesis. 391-396
• 
  Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid: Clock-frequency assignment for multiple clock domain systems-on-a-chip. 397-402
• 
  Siddharth Garg, Diana Marculescu: Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. 403-408
• 
  Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich: Interactive presentation: Reliability-aware system synthesis. 409-414

Analogue and mixed-signal design and characterization

• 
  Pengbo Sun, Ying Wei, Alex Doboli: Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators. 415-420
• 
  Gianvito Matarrese, Cristoforo Marzocca, Francesco Corsi, Stefano D'Amico, Andrea Baschirotto: Experimental validation of a tuning algorithm for high-speed filters. 421-426
• 
  Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi: Design of high-resolution MOSFET-only pipelined ADCs with digital calibration. 427-432
• 
  Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz: A new technique for characterization of digital-to-analog converters in high-speed systems. 433-438

Should you trust the surgeon or the family doctor?

• 
  Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki: DFM/DFY: should you trust the surgeon or the family doctor? 439-442

Automatic synthesis of computation intensive application specific circuits

• 
  Ajay K. Verma, Paolo Ienne: Automatic synthesis of compressor trees: reevaluating large counters. 443-448
• 
  María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida: Area optimization of multi-cycle operators in high-level synthesis. 449-454
• 
  Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon: Data-flow transformations using Taylor expansion diagrams. 455-460
• 
  Yee Jern Chong, Sri Parameswaran: Automatic application specific floating-point unit generation. 461-466
• 
  Mario Schölzel: Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP. 467-472

Embedded tutorial

• 
  Applications for ubiquitous computing and communications. 473

Automotive

• 
  Matthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel: Timing simulation of interconnected AUTOSAR software-components. 474-479
• 
  Sergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci: FPGA-based networking systems for high data-rate and reliable in-vehicle communications. 480-485
• 
  Francesco D'Ascoli, Francesco Iozzi, Corrado Marino, Massimiliano Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, Alessandro Rocchi, Marco De Marinis: Low-g accelerometer fast prototyping for automotive applications. 486-491
• 
  Riccardo Mariani, Gabriele Boschi, Federico Colucci: Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508. 492-497
• 
  Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele: Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. 498-503
• 
  Patrick Popp, Marco Di Natale, Paolo Giusto, Sri Kanajan, Claudio Pinello: Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures. 504-509

Test generation for diagnosis, scan testing and advanced memory fault models

• 
  Yu Huang: Dynamic learning based scan chain diagnosis. 510-515
• 
  Ozgur Sinanoglu, Philip Schremmer: Diagnosis, modeling and tolerance of scan chain hold-time violations. 516-521
• 
  Irith Pomeranz, Sudhakar M. Reddy: On test generation by input cube avoidance. 522-527
• 
  Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Slow write driver faults in 65nm SRAM technology: analysis and March test solution. 528-533
• 
  V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. 534-539
• 
  Kunal P. Ganeshpure, Sandip Kundu: Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. 540-545

Future design challenges

• 
  Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. 546-551
• 
  Tao Xu, Krishnendu Chakrabarty: A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays. 552-557
• 
  Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur: Reversible circuit technology mapping from non-reversible specifications. 558-563
• 
  Nicholas H. Zamora, Jung-Chun Kao, Radu Marculescu: Distributed power-management techniques for wireless network video systems. 564-569
• 
  Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli: Interactive presentation: Improving the fault tolerance of nanometric PLA designs. 570-575
• 
  Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. 576-581

Application-specific architectures

• 
  Seok-Won Seong, Prabhat Mishra: An efficient code compression technique using application-aware bitmask and dictionary selection methods. 582-587
• 
  Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar: Optimizing instruction-set extensible processors under data bandwidth constraints. 588-593
• 
  Juan Hamers, Lieven Eeckhout: Resource prediction for media stream decoding. 594-599
• 
  JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally: Register pointer architecture for efficient embedded processors. 600-605
• 
  Sven van Haastregt, Peter M. W. Knijnenburg: Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search. 606-611
• 
  Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis: Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. 612-617

Technology and process aware low power circuit design

• 
  Nikhil Jayakumar, Sunil P. Khatri: An algorithm to minimize leakage through simultaneous input vector control and circuit modification. 618-623
• 
  Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. 624-629
• 
  Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy: Process variation tolerant low power DCT architecture. 630-635
• 
  Yan Lin, Lei He: Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. 636-641

Hardware implementation of MPSoCs and NoCs architectures

• 
  André C. Nácul, Francesco Regazzoni, Marcello Lajolo: Hardware scheduling support in SMP architectures. 642-647
• 
  Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø: A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. 648-653
• 
  Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel: Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. 654-659
• 
  Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto: Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. 660-665

Hot topic I: Security and trust in ubiquitous communication (ubiquitous communication and computation special day)

• 
  Jukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen: Cost-aware capacity optimization in dynamic multi-hop WSNs. 666-671
• 
  Ingrid Verbauwhede, Patrick Schaumont: Design methods for security and trust. 672-677

Keynote: ubiquitous communication and computation special day

• 
  Heikki Huomo: Emerging solutions technology and business views for the ubiquitous communication. 678

Industrial system designs in aerospace, avionics and automotive

• 
  Louis Baguena, Emmanuel Liégeon, Alexandra Bépoix, Jean-Marc Dusserre, Christophe Oustric, Philippe Bellocq, Vincent Heiries: Development of on board, highly flexible, Galileo signal generator ASIC. 679-683
• 
  D. Hairion, S. Emeriau, E. Combot, Michel Sarlotte: New safety critical radio altimeter for airbus and related design flow. 684-688
• 
  Robert Lissel, Joachim Gerlach: Introducing new verification methods into a company's design flow: an industrial user's point of view. 689-694

Mixed-signal and RF test

• 
  Mitchell Lin, Kwang-Ting (Tim) Cheng: Testable design for advanced serial-link transceivers. 695-700
• 
  David C. Keezer, Dany Minier, Patrice Ducharme: Method for reducing jitter in multi-gigahertz ATE. 701-706
• 
  Jens Anders, Shaji Krishnan, Guido Gronthoud: Re-configuration of sub-blocks for effective application of time domain tests. 707-712
• 
  Erdem Serkan Erdogan, Sule Ozev: An ADC-BiST scheme using sequential code analysis. 713-718
• 
  Jerzy Dabrowski, Rashad Ramzan: Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique. 719-724
• 
  P. Yeung, A. Torres, P. Batra: Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor. 725-730
• 
  Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro: Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. 731-736

Embedded tutorial and panel - Heterogeneous systems on chip and systems in package

• 
  I. O'Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton, J. Hartung: Heterogeneous systems on chip and systems in package. 737-742

Novel directions in architectural simulation and validation

• 
  Ilya Wagner, Valeria Bertacco: Engineering trust with semantic guardians. 743-748
• 
  Dohyung Kim, Soonhoi Ha, Rajesh Gupta: CATS: cycle accurate transaction-driven simulation with multiple processor simulators. 749-754
• 
  Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros: A one-shot configurable-cache tuner for improved energy and performance. 755-760
• 
  Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar: Design fault directed test generation for microprocessor validation. 761-766
• 
  Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull: Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. 767-772

Power management

• 
  Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini: Adaptive power management in energy harvesting systems. 773-778
• 
  Qinru Qiu, Ying Tan, Qing Wu: Stochastic modeling and optimization for robust power management in a partially observable system. 779-784
• 
  Po-Kuan Huang, Soheil Ghiasi: Efficient and scalable compiler-directed energy optimization for realtime applications. 785-790
• 
  Linwei Niu, Gang Quan: Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systems. 791-796
• 
  Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. 797-802

Advanced techniques for embedded processors design

• 
  Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel: Instruction trace compression for rapid instruction cache simulation. 803-808
• 
  Talal Bonny, Jörg Henkel: Efficient code density through look-up table compression. 809-814
• 
  Yunsi Fei, Zhijie Jerry Shi: Microarchitectural support for program code integrity monitoring in application-specific instruction set processors. 815-820
• 
  David Sheldon, Frank Vahid, Stefano Lonardi: Interactive presentation: Soft-core processor customization using the design of experiments paradigm. 821-826

Hot topic II

• 
  Power supply and power management in Ubicom. 827

Best industrial systems designs in communication and multimedia

• 
  M. Brandenburg, A. Schöllhorn, S. Heinen, Josef Eckmueller, T. Eckart: From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teams. 828-830
• 
  Maurizio Paganini, Georg Kimmich, Stephane Ducrey, Guilhem Caubit, Vincent Coeffe: Portable multimedia SoC design: a global challenge. 831-834
• 
  Neal Wingen: What if you could design tomorrow's system today? 835-840

Nano and FIFO

• 
  Hamidreza Hashempour, Fabrizio Lombardi: Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs. 841-846
• 
  B. Jang, Y.-B. Kim, F. Lombardi: Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling. 847-852
• 
  Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters: Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. 853-858
• 
  Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters: Test quality analysis and improvement for an embedded asynchronous FIFO. 859-864
• 
  Wenjing Rao, Alex Orailoglu, Ramesh Karri: Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. 865-869

System level validation

• 
  Shan Tang, Qiang Xu: A multi-core debug platform for NoC-based systems. 870-875
• 
  Laurent Moss, Maxime de Nanclas, Luc Filion, Sebastien Fontaine, Guy Bois, El Mostapha Aboulhamid: Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. 876-881
• 
  Nicola Bombieri, Franco Fummi, Graziano Pravadelli: Incremental ABV for functional validation of TL-to-RTL design refinement. 882-887
• 
  Ioannis Mavroidis, Ioannis Papaefstathiou: Efficient testbench code synthesis for a hardware emulator system. 888-893
• 
  Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull: Interactive presentation: Implementation of a transaction level assertion framework in SystemC. 894-899
• 
  Shireesh Verma, Ian G. Harris, Kiran Ramineni: Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. 900-905

Model-based design for embedded systems

• 
  Kai Chen, Janos Sztipanovits, Sandeep Neema: Compositional specification of behavioral semantics. 906-911
• 
  Kai Huang, Lothar Thiele: Performance analysis of multimedia applications using correlated streams. 912-917
• 
  Vojtech Derbek, Christian Steger, Reinhold Weiss, Daniel Wischounig, Josef Preishuber-Pfluegl, Markus Pistauer: Simulation platform for UHF RFID. 918-923
• 
  Andreas Bauer, Markus Pister, Michael Tautschnig: Tool-support for the analysis of hybrid systems and models. 924-929
• 
  Thomas Huining Feng, Lynn Wang, Wei Zheng, Sri Kanajan, Sanjit A. Seshia: Interactive presentation: Automatic model generation for black box real-time systems. 930-935

Life begins at 65 - unless you are mixed signal

• 
  Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wassener, Navraj Nandra, Joachim Kunkel, Jose Franca, Christian Münker: Life begins at 65: unless you are mixed signal? 936-941

Resource optimisation for best effort and quality of service

• 
  Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Routing table minimization for irregular mesh NoCs. 942-947
• 
  Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten: Congestion-controlled best-effort communication for networks-on-chip. 948-953
• 
  Andreas Hansson, Martijn Coenen, Kees Goossens: Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. 954-959

Hot topic

• 
  Rajesh Galivanche, Rohit Kapur, Antonio Rubio: Testing in the year 2020. 960-965

Designs in avionics, military and space

• 
  Grégory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier: Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM. 966-971
• 
  Ingemar Söderquist: Event driven data processing architecture. 972-976
• 
  Björn Fiethe, Harald Michalik, C. Dierker, Björn Osterloh, Gang Zhou: Reconfigurable system-on-chip data processing units for space imaging instruments. 977-982
• 
  Bertrand Rousseau, Philippe Manet, D. Galerin, D. Merkenbreack, Jean-Didier Legat, F. Dedeken, Yves Gabriel: Enabling certification for dynamic partial reconfiguration using a minimal flow. 983-988
• 
  Julie Ferrigno, Philippe Perdu, Kevin Sanchez, Dean Lewis: Identification of process/design issues during 0.18 µm technology qualification for space application. 989-993
• 
  Philippe Manet, Daniel Maufroid, Leonardo Tosi, Marco Di Ciano, Olivier Mulertt, Yves Gabriel, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba: Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics. 994-999

Timing analysis and validation

• 
  Saurabh K. Tiwary, Joel R. Phillips: WAVSTAN: waveform based variational static timing analysis. 1000-1005
• 
  Shweta Srivastava, Jaijeet S. Roychowdhury: Rapid and accurate latch characterization via direct Newton solution of setup/hold times. 1006-1011
• 
  B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature and voltage aware timing analysis: application to voltage drops. 1012-1017
• 
  Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein: Accurate timing analysis using SAT and pattern-dependent delay models. 1018-1023

Model-based analysis and middleware of embedded systems

• 
  Egor R. V. Bondarev, Michel R. V. Chaudron, Peter H. N. de With: CARAT: a toolkit for design and performance analysis of component-based embedded systems. 1024-1029
• 
  E. Alessio, Franco Fummi, Davide Quaglia, Maura Turolla: Modeling and simulation alternatives for the design of networked embedded systems. 1030-1035
• 
  Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor: Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns. 1036-1041
• 
  Felix Jesús Villanueva, David Villa, Francisco Moya, Jesús Barba, Fernando Rincón, Juan Carlos López: Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networks. 1042-1047
• 
  Franco Fummi, Giovanni Perbellini, R. Pietrangeli, Davide Quaglia: Interactive presentation: A middleware-centric design flow for networked embedded systems. 1048-1053

Advanced architectures for low power optimization

• 
  Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh: Dynamic reconfiguration in sensor networks with regenerative energy sources. 1054-1059
• 
  Hwisung Jung, Massoud Pedram: Dynamic power management under uncertain information. 1060-1065
• 
  Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal: Very wide register: an asymmetric register file organization for low power embedded processors. 1066-1071
• 
  Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram: Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. 1072-1077
• 
  Pietro Babighian, Gila Kamhi, Moshe Y. Vardi: Interactive presentation: PowerQuest: trace driven data mining for power optimization. 1078-1083

Performance analysis for NoC architectures

• 
  Matthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O'Connor: System level assessment of an optical NoC in an MPSoC platform. 1084-1089
• 
  Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner: Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. 1090-1095
• 
  Ümit Y. Ogras, Radu Marculescu: Analytical router modeling for networks-on-chip performance analysis. 1096-1101
• 
  Christian Sauer, Matthias Gries, Sebastian Dirk: Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform. 1102-1107

State of the art for safety critical systems (space and aeronautics special day)

• 
  Thierry Pardessus, Heinrich Daembkes, Richard Arning: The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and space. 1108-1109

Secure systems

• 
  Johann Großschädl, Stefan Tillich, Christian Rechberger, Michael Hofmann, Marcel Medwed: Energy evaluation of software implementations of block ciphers under memory constraints. 1110-1115
• 
  Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta: An area optimized reconfigurable encryptor for AES-Rijndael. 1116-1121
• 
  Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Richard R. Brooks: Performance aware secure code partitioning. 1122-1127
• 
  Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Energy and execution time analysis of a software-based trusted platform module. 1128-1133

Reliable microarchitectures

• 
  Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai: Utilization of SECDED for soft error and variation-induced defect tolerance in caches. 1134-1139
• 
  Satish Narayanasamy, Ayse Kivilcim Coskun, Brad Calder: Transient fault prediction based on anomalies in processor events. 1140-1145
• 
  Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin: Low-cost protection for SER upsets and silicon defects. 1146-1151
• 
  Madhu Mutyam, Narayanan Vijaykrishnan: Working with process variation aware caches. 1152-1157
• 
  Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda: Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor. 1158-1163
• 
  Qiang Zhu, Aviral Shrivastava, Nikil Dutt: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. 1164-1169

Formal techniques to enhance the verification flow

• 
  In-Ho Moon, Per Bjesse, Carl Pixley: A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. 1170-1175
• 
  Daniel Große, Ulrich Kühne, Rolf Drechsler: Estimating functional coverage in bounded model checking. 1176-1181
• 
  Sean Safarpour, Andreas G. Veneris: Abstraction and refinement techniques in automated design debugging. 1182-1187
• 
  Roderick Bloem, Stefan J. Galler, Barbara Jobstmann, Nir Piterman, Amir Pnueli, Martin Weiglhofer: Interactive presentation: Automatic hardware synthesis from specifications: a case study. 1188-1193

Interconnect extraction and synthesis

• 
  Tarek Moselhy, Xin Hu, Luca Daniel: pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate. 1194-1199
• 
  Xin Hu, Tarek Moselhy, Jacob K. White, Luca Daniel: Optimization-based wideband basis functions for efficient interconnect extraction. 1200-1205
• 
  Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Thermally robust clocking schemes for 3D integrated circuits. 1206-1211
• 
  Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin: Double-via-driven standard cell library design. 1212-1217
• 
  Jingye Xu, Abinash Roy, Masud H. Chowdhury: Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. 1218-1223

Embedded tutorial/panel - A future of customizable processors: are we there yet?

• 
  Laura Pozzi, Pierre G. Paulin: A future of customizable processors: are we there yet? 1224-1225

Placement and floorplanning

• 
  Peter Spindler, Frank M. Johannes: Fast and accurate routing demand estimation for efficient routability-driven placement. 1226-1231
• 
  Paolo Azzoni, Massimo Bertoletti, Nicola Dragone, Franco Fummi, Carlo Guardiani, W. Vendraminetto: Yield-aware placement optimization. 1232-1237
• 
  Hushrav Mogal, Kia Bazargan: Microarchitecture floorplanning for sub-threshold leakage reduction. 1238-1243

Hot topic I - Industrial applications (space and aeronautics special day)

• 
  Xavier Olive, Jean-Marie Pasquet, Didier Flament: Industrial applications. 1244-1245

Keynote - Setting the industrial scene (space and aeronautics special day)

• 
  Jean Botti: Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space. 1246

Crypto blocks and security

• 
  Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen: Compact hardware design of Whirlpool hashing core. 1247-1252
• 
  Steffen Peter, Peter Langendörfer, Krzysztof Piotrowski: Flexible hardware reduction for elliptic curve cryptography in GF(2^m). 1259-1264
• 
  Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo: Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. 1265-1270

Variation tolerant mixed signal test

• 
  José Luis Rosselló, Carol de Benito, Sebastiàn A. Bota, Jaume Segura: Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. 1271-1276
• 
  Tejasvi Das, P. R. Mukund: Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry. 1277-1282
• 
  Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue: A two-tone test method for continuous-time adaptive equalizers. 1283-1288
• 
  Robert C. Aitken, Sachin Idgunji: Worst-case design and margin for embedded SRAM. 1289-1294
• 
  Michele Favalli, Cecilia Metra: Interactive presentation: Pulse propagation for the detection of small delay defects. 1295-1300
• 
  Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez: Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. 1301-1306

SAT techniques for verification

• 
  Lei Fang, Michael S. Hsiao: A new hybrid solution to boost SAT solver performance. 1307-1313
• 
  Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang: QuteSAT: a robust circuit-based SAT solver for complex circuit structure. 1313-1318
• 
  Gianpiero Cabodi, Sergio Nocco, Stefano Quer: Boosting the role of inductive invariants in model checking. 1319-1324
• 
  Daniel Kroening, Natasha Sharygina: Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs. 1325-1330

Compiler techniques for customisable architectures

• 
  Paolo Bonzini, Laura Pozzi: Polynomial-time subgraph enumeration for automated instruction set extension. 1331-1336
• 
  Mehrdad Reshadi, Daniel Gajski: Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. 1337-1342
• 
  Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim: DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. 1343-1348
• 
  Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. 1349-1354
• 
  Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock: Interactive presentation: A process splitting transformation for Kahn process networks. 1355-1360

Interconnect optimization and metastability

• 
  Suwen Yang, Mark R. Greenstreet: Computing synchronizer failure probabilities. 1361-1366
• 
  David Bañeres, Jordi Cortadella, Michael Kishinevsky: Layout-aware gate duplication and buffer insertion. 1367-1372
• 
  Min Ni, Seda Ogrenci Memik: Self-heating-aware optimal wire sizing under Elmore delay model. 1373-1378

Physical and device simulation

• 
  Amith Singhee, Rob A. Rutenbar: Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. 1379-1384
• 
  Yi Feng, Zheng Zhou, Dong Tong, Xu Cheng: Clock domain crossing fault model and coverage metric for validation of SoC design. 1385-1390
• 
  Min Chen, Wei Zhao, Frank Liu, Yu Cao: Fast statistical circuit analysis with finite-point based transistor model. 1391-1396
• 
  Wolfgang Schneider, Michael Schröter, W. Kraus, Holger Wittkopf: Interactive presentation: Statistical simulation of high-frequency bipolar circuits. 1397-1402

Hot topic II - Development and industrialization (space and aeronautics special day)

• 
  Michel Riffiod, Paul Caspi, Christophe Piala, Jean-Luc Voirin: Development and industrialisation. 1403-1405

Wireless communication and networking system implementation

• 
  Marcus Schämann, Sebastian Hessel, Ulrich Langmann, Martin Bücker: Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system. 1406-1411
• 
  Cyprian Grassmann, Mathias Richter, Mirko Sauermann: Mapping the physical layer of radio standards to multiprocessor architectures. 1412-1417
• 
  Koen Van Renterghem, P. Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu: Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. 1418-1423
• 
  Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. 1424-1429
• 
  Enrique Barajas, R. Cosculluela, D. Coutinho, Diego Mateo, J. L. González, I. Cairò, S. Banda, M. Ikeda: Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems. 1430-1435

Soft error evaluation and tolerance

• 
  Natasa Miskov-Zivanov, Diana Marculescu: Soft error rate analysis for sequential circuits. 1436-1441
• 
  Sanjit A. Seshia, Wenchao Li, Subhasish Mitra: Verification-guided soft error resilience. 1442-1447
• 
  Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro: A low-SER efficient core processor architecture for future technologies. 1448-1453
• 
  Mihir R. Choudhury, Kartik Mohanram: Accurate and scalable reliability analysis of logic circuits. 1454-1459
• 
  Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff: Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA. 1460-1465

Embedded tutorial - EDA - a pivotal theme in the european technology platforms - ARTEMIS and ENIAC

• 
  Andrew B. Kahng: Design challenges at 65nm and beyond. 1466-1467
• 
  Hermann Kopetz: The ARTEMIS cross-domain architecture for embedded systems. 1468-1469
• 
  Ahmed Amine Jerraya: HW/SW implementation from abstract architecture models. 1470-1471

Memory and instruction-set customization for real-time systems

• 
  Huynh Phung Huynh, Tulika Mitra: Instruction-set customization for real-time embedded systems. 1472-1477
• 
  Soyoung Park, Hae-woo Park, Soonhoi Ha: A novel technique to use scratch-pad memory for stack management. 1478-1483
• 
  Isabelle Puaut, Christophe Pais: Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. 1484-1489
• 
  Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Task scheduling for reliable cache architectures of multiprocessor systems. 1490-1495

Order reduction and variation-aware interconnect modelling

• 
  Ngai Wong: Fast positive-real balanced truncation of symmetric systems using cross Riccati equations. 1496-1501
• 
  Zhenhai Zhu, Joel R. Phillips: Random sampling of moment graph: a stochastic Krylov-reduction algorithm. 1502-1507
• 
  Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical model order reduction for interconnect circuits considering spatial correlations. 1508-1513
• 
  Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou: A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. 1514-1519
• 
  Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain: Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. 1520-1525

Temperature and process aware low power techniques

• 
  Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang: Accurate temperature-dependent integrated circuit leakage power estimation is easy. 1526-1531
• 
  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. 1532-1537
• 
  Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir: Maximum circuit activity estimation using pseudo-boolean satisfiability. 1538-1543
• 
  Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. 1544-1549
• 
  Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy: Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. 1550-1555

Towards total open source in aeronautics and space? (space and aeronautics special day)

• 
  Peggy Aycinena, Eric Bantegnie, Gerard Ladier, Ralph Mueller, Franco Gasperoni, Alex Wilson: Towards total open source in aeronautics and space? 1556

Wireless communication and networking algorithms

• 
  Pawel Gburzynski, Bozena Kaminska, Wladek Olesinski: A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks. 1557-1562
• 
  Gummidipudi Krishnaiah, Nur Engin, Sergei Sawitzki: Scalable reconfigurable channel decoder architecture for future wireless handsets. 1563-1568
• 
  Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan: A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems. 1569-1574
• 
  Afxendios Tychopoulos, Odysseas G. Koufopavlou: Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels. 1575-1580

System reliability and security issues

• 
  Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng: A framework for system reliability analysis considering both system error tolerance and component test quality. 1581-1586
• 
  Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria: Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. 1587-1592
• 
  Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli: Evaluation of design for reliability techniques in embedded flash memories. 1593-1598
• 
  Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: Reduction of detected acceptable faults for yield improvement via error-tolerance. 1599-1604

Statistical timing and worst-delay corner analysis

• 
  A. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song: Use of statistical timing analysis on real designs. 1605-1610
• 
  Feng Wang, Yuan Xie, Hai Ju: A novel criticality computation method in statistical timing analysis. 1611-1616
• 
  Luís Guerra e Silva, Luis Miguel Silveira, Joel R. Phillips: Efficient computation of the worst-delay corner. 1617-1622

Real-time methodologies

• 
  Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury: Accounting for cache-related preemption delay in dynamic priority schedulability analysis. 1623-1628
• 
  Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King: Energy-efficient real-time task scheduling with task rejection. 1629-1634
• 
  Liliana Cucu, Joël Goossens: Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems. 1635-1640
• 
  Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha: Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems. 1641-1646

Impact of nanometer technologies in MPSoCs and SoC design

• 
  Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi: Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. 1647-1652
• 
  Eric Humenay, David Tarjan, Kevin Skadron: Impact of process variations on multicore performance symmetry. 1653-1658
• 
  Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant: Temperature aware task scheduling in MPSoCs. 1659-1664

High-level memory and clock power optimization

• 
  Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii: Architectural leakage-aware management of partitioned scratchpad memories. 1665-1670
• 
  Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son, Ozcan Ozturk: Memory bank aware dynamic loop scheduling. 1671-1676
• 
  Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt: System level clock tree synthesis for power optimization. 1677-1682

last updated on Wed May 22 04:25:58 2013 by the dblp team
data released under the ODC-BY 1.0 license
see also our legal information page