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ORCIDChi-Ying Tsui
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- affiliation: Hong Kong University of Science and Technology
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2020 – today
- 2024
[j67]Xiaodong Meng
, Xing Li, Chi-Ying Tsui, Wing-Hung Ki, Weiqiang Liu:
A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices. IEEE J. Solid State Circuits 59(10): 3218-3231 (2024)- [c160]Jingyu He, Fengbin Tu, Kwang-Ting Cheng, Chi-Ying Tsui:
AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. DATE 2024: 1-2 - [c159]Wing-Hung Ki, Yuan Yao, Chi-Ying Tsui:
Time Domain Analysis of Secondary Stage With Series Resonance Driving Rectifier Load. ISCAS 2024: 1-4 - [c158]Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui:
Adaptive Digitally-Controlled Active Rectifier-Based Receiver for Bioimplants. ISCAS 2024: 1-5 - [c157]Fengshi Tian, Jiakun Zheng, Jingyu He, Jinbo Chen, Xiaomeng Wang, Chaoming Fang, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting Cheng:
BOLS: A Bionic Sensor-direct On-chip Learning System with Direct-Feedback-Through-Time for Personalized Wearable Health Monitoring. ISCAS 2024: 1-5 - [c156]Linping Qu, Shenghui Song, Chi-Ying Tsui, Yuyi Mao:
How Robust is Federated Learning to Communication Error? A Comparison Study Between Uplink and Downlink Channels. WCNC 2024: 1-6 - [i19]Linping Qu, Shenghui Song, Chi-Ying Tsui:
FedAQ: Communication-Efficient Federated Edge Learning via Joint Uplink and Downlink Adaptive Quantization. CoRR abs/2406.18156 (2024) - [i18]Linping Qu, Yuyi Mao, Shenghui Song, Chi-Ying Tsui:
Energy-Efficient Channel Decoding for Wireless Federated Learning: Convergence Analysis and Adaptive Design. CoRR abs/2407.13703 (2024) - 2023
- [j66]Soumitra Pal, Gajendranath Chowdary, Wing-Hung Ki, Chi-Ying Tsui:
Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications. IEEE Access 11: 20184-20195 (2023) - [j65]Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui:
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 644-657 (2023) - [j64]Xianghong Hu, Xuejiao Liu, Yu Liu, Haowei Zhang, Xijie Huang, Xihao Guan, Luhong Liang, Chi-Ying Tsui, Xiaoming Xiong, Kwang-Ting Cheng:
A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3079-3083 (2023) - [c155]Jingyu He, Ziyang Shen, Fengshi Tian, Jinbo Chen, Jie Yang, Mohamad Sawan, Hsiang-Ting Chen, Paul Bogdan, Chi-Ying Tsui:
SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks. AICAS 2023: 1-5 - [c154]Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng:
Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System. AICAS 2023: 1-5 - [c153]Jingyu He, Yucong Huang, Miguel Lastras, Terry Tao Ye, Chi-Ying Tsui, Kwang-Ting Cheng:
RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing. ASP-DAC 2023: 246-251 - [c152]Xiaodong Meng, Xing Li, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki:
A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical Devices. A-SSCC 2023: 1-3 - [c151]Fengshi Tian, Shiqi Zhao, Jingyu He, Jinbo Chen, Xiaomeng Wang, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng:
NOLS: A Near-sensor On-chip Learning System with Direct Feedback Alignment for Personalized Wearable Heart Health Monitoring. BioCAS 2023: 1-5 - [c150]Xizi Chen, Rui Pan, Xiaomeng Wang, Fengshi Tian, Chi-Ying Tsui:
Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification. DAC 2023: 1-2 - [c149]Jia Chen, Fengbin Tu, Kunming Shao, Fengshi Tian, Xiao Huo, Chi-Ying Tsui, Kwang-Ting Cheng:
AutoDCIM: An Automated Digital CIM Compiler. DAC 2023: 1-6 - [c148]Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jiakun Zheng, Hui Wu, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng:
BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare. ESSCIRC 2023: 225-228 - [c147]Syed Mohsin Abbas, Chi-Ying Tsui, Marwan Jalaleddine, Warren J. Gross:
Step-GRAND: A Low Latency Universal Soft-Input Decoder. GLOBECOM (Workshops) 2023: 1668-1673 - [c146]Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
Accelerating Large Kernel Convolutions with Nested Winograd Transformation. VLSI-SoC 2023: 1-6 - [i17]Xiaomeng Wang, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting Cheng, Chi-Ying Tsui:
A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications. CoRR abs/2307.05944 (2023) - [i16]Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross:
Step-GRAND: A Low Latency Universal Soft-input Decoder. CoRR abs/2307.07133 (2023) - [i15]Linping Qu, Shenghui Song, Chi-Ying Tsui, Yuyi Mao:
How Robust is Federated Learning to Communication Error? A Comparison Study Between Uplink and Downlink Channels. CoRR abs/2310.16652 (2023) - 2022
- [j63]Soumitra Pal, Wing-Hung Ki, Chi-Ying Tsui:
Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1560-1570 (2022) - [c145]Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, Chi-Ying Tsui:
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. AICAS 2022: 66-69 - [c144]Linping Qu, Shenghui Song, Chi-Ying Tsui:
FedDQ: Communication-Efficient Federated Learning with Descending Quantization. GLOBECOM 2022: 281-286 - [c143]Sayan Sarkar, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui:
Design Strategy of Off-Resonant Tertiary Coils for Uplink Detection in Biomedical Implants. ISCAS 2022: 156-159 - [c142]Sayan Sarkar, Jingbo Jiang, Wing-Hung Ki, Chi-Ying Tsui:
A 16-bit Encrypted On-chip Embedded System for Implantable Medical Devices. ISCAS 2022: 195-199 - 2021
- [i14]Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
A Reconfigurable Winograd CNN Accelerator with Nesting Decomposition Algorithm for Computing Convolution with Large Filters. CoRR abs/2102.13272 (2021) - [i13]Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui:
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation. CoRR abs/2104.01303 (2021) - [i12]Bo Zhang, Pedro V. Sander, Chi-Ying Tsui, Amine Bermak:
Microshift: An Efficient Image Compression Algorithm for Hardware. CoRR abs/2104.09820 (2021) - [i11]Linping Qu, Shenghui Song, Chi-Ying Tsui:
FedDQ: Communication-Efficient Federated Learning with Descending Quantization. CoRR abs/2110.02291 (2021) - 2020
- [j62]Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu:
A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique. IEEE J. Solid State Circuits 55(4): 999-1010 (2020) - [j61]Xiaopeng Zhong, Man-Kay Law, Chi-Ying Tsui, Amine Bermak:
A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing. IEEE J. Solid State Circuits 55(6): 1684-1697 (2020) - [j60]Lin Cheng, Xinyuan Ge, Langyu Hu, Yuan Yao, Wing-Hung Ki, Chi-Ying Tsui:
A 40.68-MHz Active Rectifier With Hybrid Adaptive On/Off Delay-Compensation Scheme for Biomedical Implantable Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 516-525 (2020) - [j59]Luheng Jia, Chi-Ying Tsui, Oscar C. Au, Kebin Jia:
A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference Computation. IEEE Trans. Circuits Syst. Video Technol. 30(1): 243-255 (2020) - [j58]ChenYang Xia, Chi-Ying Tsui, YouZhe Fan:
Construction of Multi-Kernel Polar Codes With Kernel Substitution. IEEE Wirel. Commun. Lett. 9(11): 1879-1883 (2020) - [c141]Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu:
Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications. ASP-DAC 2020: 1-2 - [c140]Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui:
Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation. DAC 2020: 1-6
2010 – 2019
- 2019
- [j57]Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui:
SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup. Integr. 69: 356-368 (2019) - [j56]Zizhen Zeng, Shanpu Shen, Xiaopeng Zhong, Xing Li, Chi-Ying Tsui, Amine Bermak, Ross D. Murch, Edgar Sánchez-Sinencio:
Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From -22 to 4 dBm With 99.8% Peak MPPT Power Efficiency. IEEE J. Solid State Circuits 54(9): 2601-2613 (2019) - [j55]Bo Zhang, Pedro V. Sander, Chi-Ying Tsui, Amine Bermak:
Microshift: An Efficient Image Compression Algorithm for Hardware. IEEE Trans. Circuits Syst. Video Technol. 29(11): 3430-3443 (2019) - [j54]Bo Wang, Man-Kay Law, Jun Yi, Chi-Ying Tsui, Amine Bermak:
A -12.3 dBm UHF Passive RFID Sense Tag for Grid Thermal Monitoring. IEEE Trans. Ind. Electron. 66(11): 8811-8820 (2019) - [j53]Luheng Jia, Chi-Ying Tsui, Oscar C. Au, Kebin Jia:
A New Rate-Complexity-Distortion Model for Fast Motion Estimation Algorithm in HEVC. IEEE Trans. Multim. 21(4): 835-850 (2019) - [c139]Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui:
CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation. ASP-DAC 2019: 133-139 - [c138]ChenYang Xia, YouZhe Fan, Chi-Ying Tsui:
A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes. ISCAS 2019: 1-5 - [c137]Xiaodong Meng, Xing Li, Xiaopeng Zhong, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki:
A 2.2μW 600kHz Frequency-Locked Relaxation Oscillator with 0.046%/V Voltage and 48.69ppm/°C Temperature Stability for IoT Sensor Node Applications. VLSI Circuits 2019: 44- - [c136]Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu:
A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques. VLSI Circuits 2019: 320- - [i10]ChenYang Xia, YouZhe Fan, Chi-Ying Tsui:
A Two-staged Adaptive Successive Cancellation List Decoding for Polar Codes. CoRR abs/1901.09222 (2019) - 2018
- [j52]Jiawei Zheng, Wing-Hung Ki, Chi-Ying Tsui:
Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1185-1195 (2018) - [j51]Bo Wang, Man-Kay Law, Chi-Ying Tsui, Amine Bermak:
A 10.6 pJ⋅K2 Resolution FoM Temperature Sensor Using Astable Multivibrator. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 869-873 (2018) - [j50]Xiaopeng Zhong, Bo Zhang, Amine Bermak, Chi-Ying Tsui, Man-Kay Law:
A Low-Power Compression-Based CMOS Image Sensor With Microshift-Guided SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1350-1354 (2018) - [j49]Jiawei Zheng, Wing-Hung Ki, Chi-Ying Tsui:
A Fully Integrated Analog Front End for Biopotential Signal Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3800-3809 (2018) - [j48]Mahsa Mousavi, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Bin Li, Hui Shen:
Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes. IEEE Trans. Signal Process. 66(14): 3848-3858 (2018) - [j47]ChenYang Xia, Ji Chen, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li:
A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size. IEEE Trans. Signal Process. 66(14): 3859-3874 (2018) - [c135]Lin Cheng, Xinyuan Ge, Wing-Hung Ki, Chi-Ying Tsui:
A Simplified PWM Controller for Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier. APCCAS 2018: 473-475 - [c134]Langyu Hu, Lin Cheng, Yuan Yao, Tak-Sang Yim, Wing-Hung Ki, Chi-Ying Tsui:
A 40.68MHz Active Rectifier with Hybrid Delay Compensation Scheme. APCCAS 2018: 501-504 - [c133]Yuan Yao, Xiaodong Meng, Chi-Ying Tsui, Wing-Hung Ki:
Polyimide-Based Flexible 3-Coil Inductive Link Design and Optimization. APCCAS 2018: 505-508 - [c132]Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui:
A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization. ASP-DAC 2018: 123-128 - [c131]Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity. DATE 2018: 241-244 - [c130]Xiaodong Meng, Xing Li, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki:
An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector. ISCAS 2018: 1-5 - [c129]ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
On Path Memory in List Successive Cancellation Decoder of Polar Codes. ISCAS 2018: 1-5 - [c128]Qian Yu, Farid Boussaïd, Amine Bermak, Chi-Ying Tsui:
Room-Temperature Dual-mode CMOS Gas-FET Sensor for Diabetes Detection. ISCAS 2018: 1-4 - [c127]Xiaopeng Zhong, Qian Yu, Amine Bermak, Chi-Ying Tsui, May-Kay Law:
A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection. VLSI Circuits 2018: 247-248 - [i9]ChenYang Xia, Ji Chen, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li:
A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder with Large List Size. CoRR abs/1805.02916 (2018) - [i8]YouZhe Fan, ChenYang Xia, Ji Chen, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li:
A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes. CoRR abs/1806.11301 (2018) - 2017
- [j46]Lin Cheng, Wing-Hung Ki, Chi-Ying Tsui:
A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier. IEEE J. Solid State Circuits 52(5): 1412-1423 (2017) - [j45]Xing Li, Yin-Ping Li, Chi-Ying Tsui, Wing-Hung Ki:
Wireless Power Transfer System With ΣΔ-Modulated Transmission Power and Fast Load Response for Implantable Medical Devices. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 279-283 (2017) - [j44]Jiawei Zheng, Wing-Hung Ki, Langyu Hu, Chi-Ying Tsui:
Chopper Capacitively Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1392-1396 (2017) - [j43]Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1098-1111 (2017) - [c126]Lin Cheng, Wing-Hung Ki, Chi-Ying Tsui:
A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications. ASP-DAC 2017: 33-34 - [c125]Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques. ASP-DAC 2017: 690-695 - [c124]ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, ChongYang Zeng, Jie Jin, Bin Li:
An implementation of list successive cancellation decoder with large list size for polar codes. FPL 2017: 1-4 - [c123]Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
Concatenated LDPC-polar codes decoding through belief propagation. ISCAS 2017: 1-4 - [c122]Feng Gao, Amine Bermak, Chi-Ying Tsui, Farid Boussaïd:
Dual transduction Gas sensor based on a surface acoustic wave resonator. ISCAS 2017: 1-4 - [c121]Xiaopeng Zhong, Amine Bermak, Chi-Ying Tsui:
A low-offset dynamic comparator with area-efficient and low-power offset cancellation. VLSI-SoC 2017: 1-6 - [i7]Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
Concatenated LDPC-Polar Codes Decoding Through Belief Propagation. CoRR abs/1703.05542 (2017) - [i6]Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
SparseNN: An Energy-Efficient Neural Network Accelerator Exploiting Input and Output Sparsity. CoRR abs/1711.01263 (2017) - [i5]ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
On Path Memory in List Successive Cancellation Decoder of Polar Codes. CoRR abs/1712.02053 (2017) - 2016
- [j42]Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
BiLink: A high performance NoC router architecture using bi-directional link with double data rate. Integr. 55: 30-42 (2016) - [j41]YouZhe Fan, ChenYang Xia, Ji Chen, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li:
A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes. IEEE J. Sel. Areas Commun. 34(2): 303-317 (2016) - [j40]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 471-484 (2016) - [j39]Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling. ACM Trans. Design Autom. Electr. Syst. 21(3): 52:1-52:38 (2016) - [c120]Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. ASP-DAC 2016: 581-586 - [c119]Ji Chen, YouZhe Fan, ChenYang Xia, Chi-Ying Tsui, Jie Jin, Kai Chen, Bin Li:
Low-Complexity List Successive-Cancellation Decoding of Polar Codes Using List Pruning. GLOBECOM 2016: 1-6 - [c118]Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross:
Hardware decoders for polar codes: An overview. ISCAS 2016: 149-152 - [c117]Jiawei Zheng, Wing-Hung Ki, Chi-Ying Tsui:
A low-power chopper bandpass amplifier for biopotential sensors. ISCAS 2016: 301-304 - [c116]Xiaodong Meng, Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
An indoor solar energy harvesting system using dual mode SIDO converter with fully digital time-based MPPT. ISCAS 2016: 2354-2357 - [c115]Zizhen Zeng, Xing Li, Amine Bermak, Chi-Ying Tsui, Wing-Hung Ki:
A WLAN 2.4-GHz RF energy harvesting system with reconfigurable rectifier for wireless sensor network. ISCAS 2016: 2362-2365 - [c114]Lin Cheng, Wing-Hung Ki, Tat-To Wong, Tak-Sang Yim, Chi-Ying Tsui:
21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifier. ISSCC 2016: 376-377 - [c113]Syed Mohsin Abbas, Chi-Ying Tsui:
Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. VLSI-SoC 2016: 1-5 - [c112]Syed Mohsin Abbas, Chi-Ying Tsui:
Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO. VLSI-SoC (Selected Papers) 2016: 192-212 - [e2]Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis:
VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers. IFIP Advances in Information and Communication Technology 483, Springer 2016, ISBN 978-3-319-46096-3 [contents] - [i4]Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross:
Hardware Decoders for Polar Codes: An Overview. CoRR abs/1606.00737 (2016) - 2015
- [j38]Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices. IEEE J. Solid State Circuits 50(4): 978-989 (2015) - [j37]Xing Li, Xiaodong Meng, Chi-Ying Tsui, Wing-Hung Ki:
Reconfigurable Resonant Regulating Rectifier With Primary Equalization for Extended Coupling- and Loading-Range in Bio-Implant Wireless Power Transfer. IEEE Trans. Biomed. Circuits Syst. 9(6): 875-884 (2015) - [j36]Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 617-624 (2015) - [j35]Zhiliang Qian, Syed Mohsin Abbas, Chi-Ying Tsui:
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1854-1867 (2015) - [c111]YouZhe Fan, Ji Chen, ChenYang Xia, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li:
Low-latency list decoding of polar codes with double thresholding. ICASSP 2015: 1042-1046 - [c110]Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
UHF energy harvesting system using reconfigurable rectifier for wireless sensor network. ISCAS 2015: 93-96 - [c109]Luheng Jia, Chi-Ying Tsui, Oscar C. Au, Amin Zheng:
A fast variable block size motion estimation algorithm with refined search range for a two-layer data reuse scheme. ISCAS 2015: 1206-1209 - [c108]Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications. ISSCC 2015: 1-3 - [c107]Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
Low complexity belief propagation polar code decoder. SiPS 2015: 1-6 - [c106]Youngsoo Shin, Chi-Ying Tsui:
Message from the technical program chairs. VLSI-SoC 2015: IX - [i3]YouZhe Fan, Ji Chen, ChenYang Xia, Chi-Ying Tsui, Jie Jin, Hui Shen, Bin Li:
Low-latency List Decoding Of Polar Codes With Double Thresholding. CoRR abs/1504.03437 (2015) - [i2]Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
Low Complexity Belief Propagation Polar Code Decoders. CoRR abs/1505.04979 (2015) - 2014
- [j34]YouZhe Fan, Chi-Ying Tsui:
An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation. IEEE Trans. Signal Process. 62(12): 3165-3179 (2014) - [j33]Hui Shao, Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1693-1704 (2014) - [c105]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
A comprehensive and accurate latency model for Network-on-Chip performance analysis. ASP-DAC 2014: 323-328 - [c104]Yuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui:
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. DAC 2014: 104:1-104:6 - [c103]YouZhe Fan, Chi-Ying Tsui:
Low-latency MAP demapper architecture for coded modulation with iterative decoding. ISCAS 2014: 730-733 - [c102]Xing Li, Yan Lu, Chi-Ying Tsui, Wing-Hung Ki:
An adaptive wireless powering and data telemetry system for optic nerve stimulation. ISCAS 2014: 1404-1407 - [c101]Luheng Jia, Oscar C. Au, Chi-Ying Tsui, Wei Dai, Pengfei Wan:
A fast intermode decision algorithm based on analysis of inter prediction residual. MMSP 2014: 1-4 - [c100]Yuankun Xue, Zhiliang Qian, Guopeng Wei, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms. NOCS 2014: 17-24 - [c99]Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devices. VLSIC 2014: 1-2 - 2013
- [j32]Chi-Ying Tsui, Xing Li, Wing-Hung Ki:
Energy Harvesting and Power Delivery for Implantable Medical Devices. Found. Trends Electron. Des. Autom. 7(3): 179-246 (2013) - [c98]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. DATE 2013: 354-357 - [c97]Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial). ICCAD 2013: 82-84 - [c96]Luheng Jia, Oscar C. Au, Chi-Ying Tsui, Yongfang Shi, Rui Ma, Hong Zhang:
A diamond search windowbased adaptive search range algorithm. ICME Workshops 2013: 1-4 - [c95]Yan Lu, Xing Li, Wing-Hung Ki, Chi-Ying Tsui, C. Patrick Yue:
A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices. ISSCC 2013: 66-67 - 2012
- [c94]Zhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu:
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. CODES+ISSS 2012: 161-170 - [c93]Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui:
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. DATE 2012: 1295-1300 - [c92]Ricky Yiu-kee Choi, Chi-Ying Tsui:
A novel offset cancellation technique for dynamic comparator latch. MWSCAS 2012: 614-617 - [c91]YouZhe Fan, Chi-Ying Tsui:
Low-Complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard. VTC Fall 2012: 1-5 - [e1]Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy:
VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers. IFIP Advances in Information and Communication Technology 379, Springer 2012, ISBN 978-3-642-32769-8 [contents] - 2011
- [j31]Hui Shao, Xing Li, Chi-Ying Tsui:
Low energy multi-stage level converter for sub-threshold logic. IET Comput. Digit. Tech. 5(5): 375-385 (2011) - [j30]Chao Lu, Chi-Ying Tsui, Wing-Hung Ki:
Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2109-2119 (2011) - [c90]Zhiliang Qian, Chi-Ying Tsui:
A thermal-aware application specific routing algorithm for Network-on-Chip design. ASP-DAC 2011: 449-454 - [c89]YouZhe Fan, James She, Chi-Ying Tsui:
Efficient iterative receiver for LDPC coded wireless IPTV system. ICIP 2011: 953-956 - [c88]Denis Guangyin Chen, Amine Bermak, Chi-Ying Tsui:
A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors. ISCAS 2011: 2825-2828 - [c87]Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui:
Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications. VLSI-SoC (Selected Papers) 2011: 158-186 - [c86]Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui:
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. VLSI-SoC 2011: 192-195 - [c85]Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui:
A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. VLSI-SoC 2011: 296-301 - [c84]Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui:
Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. VLSI-SoC 2011: 374-379 - 2010
- [j29]Jun Yin, Jun Yi, Matthew K. Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew M. F. Yuen:
A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. IEEE J. Solid State Circuits 45(11): 2404-2420 (2010) - [j28]Jie Jin, Chi-Ying Tsui:
An Energy Efficient Layered Decoding Architecture for LDPC Decoder. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1185-1195 (2010) - [j27]Feng Liu, Chi-Ying Tsui, Ying Jun Zhang:
Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks. IEEE Trans. Wirel. Commun. 9(7): 2258-2267 (2010) - [c83]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design. ASP-DAC 2010: 75-80 - [c82]Yunxiao Ling, Jun Yi, Chi-Ying Tsui, Wing-Hung Ki:
System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling. ISCAS 2010: 3012-3015 - [c81]Jun Yin, Jun Yi, Man Kay Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen:
A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. ISSCC 2010: 308-309 - [c80]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control. VLSI-SoC 2010: 167-172
2000 – 2009
- 2009
- [j26]Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation. IEEE J. Solid State Circuits 44(4): 1112-1120 (2009) - [j25]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1138-1142 (2009) - [c79]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
An inductor-less MPPT design for light energy harvesting systems. ASP-DAC 2009: 101-102 - [c78]Hui Shao, Chi-Ying Tsui:
Low energy level converter design for sub-Vth logics. ASP-DAC 2009: 107-108 - [c77]Ricky Yiu-kee Choi, Chi-Ying Tsui:
A Low Energy Two-step Successive Approximation Algorithm for ADC Design. ISCAS 2009: 17-20 - [c76]Jie Jin, Chi-Ying Tsui:
Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition. ISCAS 2009: 2233-2236 - [c75]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. ISLPED 2009: 69-74 - 2008
- [j24]Chi-Ying Tsui, Robert Yi-Ching Au, Ricky Yiu-kee Choi:
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping. Integr. 41(1): 76-86 (2008) - [j23]Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications. IEEE J. Solid State Circuits 43(4): 815-822 (2008) - [j22]Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Sau-Wing Man, Howard C. Luong, Vincent K. N. Lau, Chi-Ying Tsui:
A Single-Chip UHF RFID Reader in 0.18 µm CMOS Process. IEEE J. Solid State Circuits 43(8): 1741-1754 (2008) - [c74]Ngok-Man Sze, Wing-Hung Ki, Chi-Ying Tsui:
Threshold Voltage Start-up Boost Converter for Sub-mA Applications. DELTA 2008: 338-341 - [c73]Ngok-Man Sze, Feng Su, Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui:
Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications. ISCAS 2008: 2218-2221 - [c72]Jun Yi, Feng Su, Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui:
An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting. ISCAS 2008: 2570-2573 - [c71]Jie Jin, Chi-Ying Tsui:
A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. ISLPED 2008: 253-258 - [c70]Ricky Yiu-kee Choi, Chi-Ying Tsui:
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. ISQED 2008: 317-320 - 2007
- [j21]Jun Yi, Wing-Hung Ki, Chi-Ying Tsui:
Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(1): 153-166 (2007) - [j20]Jun Yi, Wing-Hung Ki, Chi-Ying Tsui:
Corrections to "Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications" [Jan 07 153-166]. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(6): 1406 (2007) - [j19]Hing Mo Lam, Chi-Ying Tsui:
A mux-based High-Performance Single-Cycle CMOS Comparator. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 591-595 (2007) - [j18]Jie Jin, Chi-Ying Tsui:
Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1172-1176 (2007) - [c69]Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Adam S. W. Man, Howard C. Luong, Vincent Kin Nang Lau, Chi-Ying Tsui:
Single-Chip UHF RFID reader in 0.18- μm CMOS. CICC 2007: 111-114 - [c68]Lap-Fai Leung, Chi-Ying Tsui:
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. DAC 2007: 128-131 - [c67]Hui Shao, Chi-Ying Tsui:
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic. ESSCIRC 2007: 312-315 - [c66]Chao Lu, Chi-Ying Tsui, Wing-Hung Ki:
A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications. ISCAS 2007: 1349-1352 - [c65]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications. ISCAS 2007: 1353-1356 - [c64]Adam S. W. Man, Edward S. Zhang, Hin-Tat Chan, Vincent K. N. Lau, Chi-Ying Tsui, Howard C. Luong:
Design and Implementation of a Low-power Baseband-system for RFID Tag. ISCAS 2007: 1585-1588 - [c63]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
A micro power management system and maximum output power control for solar energy harvesting applications. ISLPED 2007: 298-303 - [c62]Chao Lu, Chi-Ying Tsui, Wing-Hung Ki:
Vibration energy scavenging and management for ultra low power applications. ISLPED 2007: 316-321 - [c61]Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao:
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. VLSI Design 2007: 830-835 - [i1]Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. CoRR abs/0710.4758 (2007) - 2006
- [j17]Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui:
Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices. IEEE Trans. Circuits Syst. II Express Briefs 53-II(12): 1378-1382 (2006) - [c60]Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su:
Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. ASP-DAC 2006: 96-97 - [c59]Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui:
Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. ASP-DAC 2006: 102-103 - [c58]Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui:
Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. ASP-DAC 2006: 104-105 - [c57]Lap-Fai Leung, Chi-Ying Tsui:
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. DAC 2006: 833-838 - [c56]Hing-mo Lam, Chi-Ying Tsui:
High performance single clock cycle CMOS comparator. ISCAS 2006 - [c55]Feng Liu, Chi-Ying Tsui:
Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time. ISCAS 2006 - [c54]Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
A charge based computation system and control strategy for energy harvesting applications. ISCAS 2006 - [c53]Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
High efficiency cross-coupled doubler with no reversion loss. ISCAS 2006 - [c52]Jie Jin, Chi-Ying Tsui:
A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. ISLPED 2006: 406-411 - [c51]Jin Jie, Chi-Ying Tsui:
Low Complexity SST Viterbi Decoder. VTC Fall 2006: 1-2 - 2005
- [j16]Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui:
A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation. IEEE J. Solid State Circuits 40(3): 772-780 (2005) - [c50]Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. DATE 2005: 634-639 - [c49]Feng Liu, Chi-Ying Tsui:
A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images. ESTIMedia 2005: 21-26 - [c48]Wing-Hung Ki, Feng Su, Chi-Ying Tsui:
Charge redistribution loss consideration in optimal charge pump design. ISCAS (2) 2005: 1895-1898 - [c47]Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Gate control strategies for high efficiency charge pumps. ISCAS (2) 2005: 1907-1910 - [c46]Jin Jie, Chi-Ying Tsui, Wai Ho Mow:
A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. ISCAS (4) 2005: 3359-3362 - 2004
- [j15]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui:
An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction. IEEE J. Solid State Circuits 39(1): 140-149 (2004) - [c45]Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow:
Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. ASP-DAC 2004: 125-130 - [c44]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui:
Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. ASP-DAC 2004: 539-540 - [c43]Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui:
A dual-band switching digital controller for a buck converter. ASP-DAC 2004: 561-562 - [c42]Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki:
Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. ASP-DAC 2004: 647-652 - [c41]Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki:
Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data. ASP-DAC 2004: 663-665 - [c40]Siu-Kei Wong, Chi-Ying Tsui:
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. DATE 2004: 130-135 - [c39]Feng Liu, Chi-Ying Tsui:
Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication. ESTIMedia 2004: 81-86 - [c38]Robert Yi-Ching Au, Chi-Ying Tsui:
Least leakage vector assisted technology mapping for total power optimization. ISCAS (5) 2004: 145-148 - [c37]Siu-Kei Wong, Chi-Ying Tsui:
Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. ISCAS (2) 2004: 321-324 - [c36]Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. PATMOS 2004: 553-563 - 2003
- [j14]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok:
Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode. IEEE J. Solid State Circuits 38(1): 89-100 (2003) - [j13]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui:
A pseudo-CCM/DCM SIMO switching converter with freewheel switching. IEEE J. Solid State Circuits 38(6): 1007-1014 (2003) - [c35]Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui:
Design and implementation of high-speed arbiter for large scale VOQ crossbar switches. ISCAS (2) 2003: 308-311 - [c34]Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki:
Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. ISCAS (5) 2003: 309-312 - [c33]Hing-mo Lam, Chi-Ying Tsui:
High performance and low power completion detection circuit. ISCAS (5) 2003: 405-408 - [c32]Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok:
Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation. ISCAS (3) 2003: 447-450 - 2002
- [c31]Jing Liu, Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui:
Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches. Hot Interconnects 2002: 43-51 - [c30]Kwan-wai Wong, Chi-Ying Tsui, Roger S.-K. Cheng, Wai Ho Mow:
A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels. ISCAS (3) 2002: 273-276 - [c29]Yan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow:
Low complexity OFDM receiver using Log-FFT for coded OFDM system. ISCAS (3) 2002: 445-448 - [c28]Yan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow:
Performance study of OFDM receiver using FFT based on log number system. VTC Spring 2002: 1257-1259 - 2001
- [j12]Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S.-K. Cheng:
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 34-41 (2001) - [c27]Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok:
A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. ASP-DAC 2001: 19-20 - [c26]Dongsheng Ma, Wing-Hung Ki, Philip K. T. Mok, Chi-Ying Tsui:
Single-inductor multiple-output switching converters with bipolar outputs. ISCAS (3) 2001: 301-304 - 2000
- [j11]Zhong-Li He, Chi-Ying Tsui, Kai-Keung Chan, Ming L. Liou:
Low-power VLSI design for motion estimation using adaptive pixel truncation. IEEE Trans. Circuits Syst. Video Technol. 10(5): 669-678 (2000) - [j10]Chi-Ying Tsui, Roger S.-K. Cheng, Curtis Ling:
Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications. Wirel. Pers. Commun. 14(1): 49-64 (2000) - [c25]Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S. Cheng:
VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. ASP-DAC 2000: 3-4 - [c24]Chi-Ying Tsui, Louis Chung-Yin Kwan, Chin-Tau Lea:
VLSI implementation of a switch fabric for mixed ATM and IP traffic. ASP-DAC 2000: 5-6 - [c23]Billy Chi-Kin Poon, Chi-Ying Tsui, Roger S. Cheng:
Composite interference cancellation scheme for CDMA systems. GLOBECOM 2000: 1-5 - [c22]Yan Wang, Chi-Ying Tsui, Roger Shu-Kwan Cheng:
A reduced complexity implementation of the Log-Map algorithm for turbo-codes decoding. ICASSP 2000: 2621-2624 - [c21]Yan Wang, Chi-Ying Tsui, Roger S. Cheng:
A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme. ISCAS 2000: 283-286 - [c20]Bob Ka-Man Wong, Chi-Ying Tsui, Roger S.-K. Cheng:
Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme. ISCAS 2000: 365-368 - [c19]Wong Kwan Wai, Chi-Ying Tsui, Roger S. Cheng:
A low complexity architecture of the V-BLAST system. WCNC 2000: 310-314
1990 – 1999
- 1999
- [j9]Chin-Tau Lea, Chi-Ying Tsui, Bo Li, C.-Y. Kwan, Stanley K.-M. Chan, Angus H.-W. Chan:
A/I Net: a network that integrates ATM and IP. IEEE Netw. 13(1): 48-55 (1999) - [c18]Massoud Pedram, Chi-Ying Tsui, Qing Wu:
An Integrated Battery-Hardware Model for Portable Electronics. ASP-DAC 1999: 109- - [c17]Chun-hong Chen, Chi-Ying Tsui:
Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC 1999: 233-236 - [c16]Chi-Ying Tsui, Roger Shu-Kwan Cheng, Curtis Ling:
Low power ACS unit design for the Viterbi decoder [CDMA wireless systems]. ISCAS (1) 1999: 137-140 - [c15]Wai-Kwong Lee, Chi-Ying Tsui:
Finite state machine partitioning for low power. ISCAS (1) 1999: 306-309 - [c14]Chi Wai Yung, Hung Fai Fu, Chi-Ying Tsui, Roger S. Cheng, D. George:
Unequal error protection for wireless transmission of MPEG audio. ISCAS (6) 1999: 342-345 - [c13]Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng:
Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. ISLPED 1999: 36-41 - [c12]Sai Kit Lai, Roger S. Cheng, Khaled Ben Letaief, Chi-Ying Tsui:
Adaptive tracking of optimal bit and power allocation for OFDM systems in time-varying channels. WCNC 1999: 776-780 - 1998
- [j8]Zhong-Li He, Ming L. Liou, Philip C. H. Chan, Chi-Ying Tsui:
Generic VLSI architecture for block-matching motion estimation algorithms. Int. J. Imaging Syst. Technol. 9(4): 257-273 (1998) - [j7]Chi-Ying Tsui, Massoud Pedram:
Accurate and efficient power simulation strategy by compacting the input vector set. Integr. 25(1): 37-52 (1998) - [j6]Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram:
Gate-level power estimation using tagged probabilistic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1099-1107 (1998) - [j5]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
Low-power state assignment targeting two- and multilevel logic implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1281-1291 (1998) - [c11]Chun-hong Chen, Chi-Ying Tsui:
Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED 1998: 24-29 - 1997
- [c10]Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram:
A Power Estimation Framework for Designing Low Power Portable Video Applications. DAC 1997: 421-424 - [c9]Xiao-Dong Zhang, Chi-Ying Tsui:
An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms. ICASSP 1997: 603-606 - [c8]Zhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L. Liou:
Low power motion estimation design using adaptive pixel truncation. ISLPED 1997: 167-172 - 1996
- [j4]Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin:
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. 4(4): 495 (1996) - [c7]Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram:
Improving the Efficiency of Power Simulators by Input Vector Compaction. DAC 1996: 165-168 - 1995
- [j3]Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin:
Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 404-416 (1995) - 1994
- [j2]Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain:
Saving Power in the Control Path of Embedded Processors. IEEE Des. Test Comput. 11(4): 24-30 (1994) - [j1]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1110-1122 (1994) - [c6]Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain:
Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. COMPCON 1994: 489-498 - [c5]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. DAC 1994: 18-23 - [c4]Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain:
Low power state assignment targeting two-and multi-level logic implementations. ICCAD 1994: 82-87 - 1993
- [c3]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
Technology Decomposition and Mapping Targeting Low Power Dissipation. DAC 1993: 68-73 - [c2]Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
Efficient estimation of dynamic power consumption under a real delay model. ICCAD 1993: 224-228 - 1992
- [c1]Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain:
Application-Driven Design Automation for Microprocessor Design. DAC 1992: 512-517
Coauthor Index
Kwang-Ting Cheng
aka: Kwang-Ting (Tim) Cheng
aka: Kwang-Ting (Tim) Cheng
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