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ORCIDISSCC 2010: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010. IEEE 2010, ISBN 978-1-4244-6033-5
Paper Sessions
Plenary Session
- Jiri Marek:
MEMS for automotive and consumer electronics. 9-17 - Greg Delagi:
Harnessing technology to advance the next-generation mobile user-experience. 18-24 - Tomoyuki Suzuki:
Challenges of image-sensor development. 27-30 - James D. Meindl, Azad Naeemi
, Muhannad S. Bakir, R. Murali:
Nanoelectronics in retrospect, prospect and principle. 31-35
mm-Wave Beamforming & RF Building Blocks
- Ta-Shun Chu, Hossein Hashemi:
A true time-delay-based bandpass multi-beam array at mm-waves supporting instantaneously wide bandwidths. 38-39 - Kuba Raczkowski, Walter De Raedt, Bart Nauwelaers, Piet Wambacq:
A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS. 40-41 - Wei L. Chan, John R. Long, Marco Spirito, John J. Pekarik:
A 60GHz-band 2×2 phased-array transmitter in 65nm CMOS. 42-43 - Hua Wang, Constantine Sideris, Ali Hajimiri:
A 5.2-to-13GHz class-AB CMOS power amplifier with a 25.2dBm peak output power at 21.6% PAE. 44-45 - Caroline Andrews, Alyosha C. Molnar:
A passive-mixer-first receiver with baseband-controlled RF impedance matching, ≪ 6dB NF, and ≫ 27dBm wideband IIP3. 46-47 - Luca Fanori, Antonio Liscidini, Rinaldo Castello:
3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL. 48-49 - Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita:
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. 50-51 - Daniel J. Yeager, Fan Zhang, Azin Zarrasvand, Brian P. Otis:
A 9.2µA gen 2 compatible UHF RFID sensing tag with -12dBm Sensitivity and 1.25µVrms input-referred noise floor. 52-53
Cellular Techniques
- Thomas Dellsperger, David Tschopp, Jürgen Rogin, Yangjian Chen, Thomas Burger, Qiuting Huang:
A quad-band class-39 RF CMOS receiver for evolved EDGE. 56-57 - Jaimin Mehta, Robert Bogdan Staszewski, Oren E. Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer K. Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru:
A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC. 58-59 - Qiuting Huang, Jürgen Rogin, Xinhua Chen, David Tschopp, Thomas Burger, Thomas Christen, Dimitris Papadopoulos, Ilian Kouchev, Chiara Martelli, Thomas Dellsperger:
A tri-band SAW-less WCDMA/HSPA RF CMOS transceiver with on-chip DC-DC converter connectable to battery. 60-61 - Xin He, Jan van Sinderen, Robert Rutten:
A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end. 62-63 - Kimmo Koli, Jarkko Jussila, Pete Sivonen, Sami Kallioinen, Aarno Pärssinen:
A 900MHz direct ΔΣ receiver in 65nm CMOS. 64-65 - Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe:
A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization. 66-67 - Hyunwon Moon, Sangyoub Lee, Seung-Chan Heo, Hwayeal Yu, Jinhyuck Yu, Ji-Soo Chang, Seung-Il Choi, Byeong-Ha Park:
A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS. 68-69 - Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Nobuyuki Itoh, Peter R. Kinget:
A low-power low-noise direct-conversion front-end with digitally assisted IIP2 background self calibration. 70-71
Analog Techniques
- Mahdi Kashmiri, Michiel A. P. Pertijs, Kofi A. A. Makinwa:
A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C. 74-75 - Massimiliano Belloni, Edoardo Bonizzoni, Andrea Fornasari, Franco Maloberti:
A micropower chopper-correlated double-sampling amplifier with 2µV standard deviation offset and 37nV/√Hz input noise density. 76-77 - Guang Ge, Cheng Zhang, Gian Hoogzaad, Kofi A. A. Makinwa:
A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from -40°C to 125°C. 78-79 - Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
A 21nV/√Hz chopper-stabilized multipath current-feedback instrumentation amplifier with 2µV offset. 80-81 - Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu:
A 10mW stereo audio CODEC in 0.13µm CMOS. 82-83 - Alex Lollio, Giacomino Bollati, Rinaldo Castello:
Class-G headphone driver in 65nm CMOS technology. 84-85 - Sreekiran Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi:
45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNR. 86-87 - Chul Kim, Chang-Seok Chae, Young-sub Yuk, Yi-Gyeong Kim, Jong-Kee Kwon, Gyu-Hyeong Cho:
A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS. 88-89 - Eoin O'hAnnaidh, Emmanuel Rouat, Sarah Verhaeren, Stéphane Le Tual, Christophe Garnier:
A 3.2GHz-sample-rate 800mHz bandwidth highly reconfigurable analog FIR filter in 45nm CMOS. 90-91 - Vaibhav Maheshwari, Wouter A. Serdijn, John R. Long, John J. Pekarik:
A 34dB SNDR instantaneously-companding baseband SC filter for 802.11a/g WLAN receivers. 92-93
Processors
- Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury:
Westmere: A family of 32nm IA processors. 96-97 - Jinuk Luke Shin, Kenway W. Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Penny Li, Alan P. Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong:
A 40nm 16-core 128-thread CMT SPARC SoC processor. 98-99 - Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. 100-101 - Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban:
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. 102-103 - Charles L. Johnson, David H. Allen, Jeffrey D. Brown, Steve Vanderwiel, Russ Hoover, Heather D. Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenidis, Claude Basso:
A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. 104-105 - Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, Amy Novak, Sam Naffziger:
An x86-64 core implemented in 32nm SOI CMOS. 106-107 - Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson:
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. 108-109 - Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. 110-111
Displays & Biomedical Devices
- Hyoung-Rae Kim, Yoon-Kyung Choi, San-Ho Byun, Sang-Woo Kim, Kwang-Ho Choi, Hae-Yong Ahn, Jong Kang Park, Dong-Yul Lee, Zhong-Yuan Wu, Hyung-Dal Kwon, Yong-Yeob Choi, Chang-Ju Lee, Hwa-Hyun Cho, Jae-Suk Yu, Myunghee Lee:
A mobile-display-driver IC embedding a capacitive-touch-screen controller system. 114-115 - Seok-in Hong, Jin-Wook Han, Dong-Hee Kim, Oh-Kyong Kwon:
A double-loop control LED backlight driver IC for medium-sized LCDs. 116-117 - G. Reza Chaji, Stefan Alexander, J. Marcel Dionne, Yaser Azizi, Corbin Church, John Hamer, Jeff Spindler, Arokia Nathan:
Stable RGBW AMOLED display with OLED degradation compensation using electrical feedback. 118-119 - Seung Bae Lee, Hyung-Min Lee, Mehdi Kiani, Uei-Ming Jow, Maysam Ghovanloo:
An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications. 120-121 - Zhiming Xiao, Chun-Ming Tang, Christopher M. Dougherty, Rizwan Bashirullah:
A 20µW neural recording tag with supply-current-modulated AFE in 0.13µm CMOS. 122-123 - Refet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Patrick Merken, Chris Van Hoof:
A 30µW Analog Signal Processor ASIC for biomedical signal monitoring. 124-125 - Xiaodan Zou, Wen-Sin Liew, Libin Yao, Yong Lian:
A 1V 22µW 32-channel implantable EEG recording IC. 126-127 - Kim Fung Edward Lee:
A timing controlled AC-DC converter for biomedical implants. 128-129 - Arun Manickam, Aaron Chevalier, Mark W. McDermott, Andrew D. Ellington, Arjang Hassibi:
A CMOS electrochemical impedance spectroscopy biosensor array for label-free biomolecular detection. 130-131
Designing in Emerging Technologies
- Wei Xiong, Ute Zschieschang, Hagen Klauk, Boris Murmann:
A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass. 134-135 - Hagen Marien, Michiel Steyaert, Nick A. J. M. van Aerle, Paul Heremans:
An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision. 136-137 - Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects. 138-139 - Kris Myny, Monique J. Beenhakkers, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
Robust digital design in organic electronics by dual-gate technology. 140-141 - David Da He, Ivan Nausieda, Kyungbum Kevin Ryu, Akintunde Ibitayo Akinwande, Vladimir Bulovic, Charles G. Sodini:
An integrated organic circuit array for flexible large-area temperature sensing. 142-143 - Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. 144-145 - Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki:
A wafer-level heterogeneous technology integration for flexible pseudo-SoC. 146-147 - Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne:
Design issues and considerations for low-cost 3D TSV IC technology. 148-149 - Fred Chen, Matthew Spencer, Rhesa Nathanael, Chengcheng Wang, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu-Jae King Liu, Dejan Markovic, Vladimir Stojanovic, Elad Alon:
Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications. 150-151 - Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam G. Shahidi:
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. 152-153
High-Speed Wireline Transceivers
- Frank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. 156-157 - Masum Hossain, Anthony Chan Carusone:
A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS. 158-159 - Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. 160-161 - Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno:
A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. 162-163 - Massimo Pozzoni, Simone Erba, Davide Sanzogni, Marcello Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi, Giorgio Spelgatti, Francesco Svelto:
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. 164-165 - Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto:
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. 166-167 - Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh:
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. 168-169 - Sameh A. Ibrahim, Behzad Razavi:
A 20Gb/s 40mW equalizer in 90nm CMOS technology. 170-171
Digital Circuits & Sensors
- Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. 174-175 - Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner, Ken Chang:
Low-skew clock distribution using zero-phase-clock-buffer DLLs. 176-177 - James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski:
POWER7TM local clocking and clocked storage elements. 178-179 - Cheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang, Tejpal Singh, Jim Vash, Bo Wang, Tom Wang:
A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor. 180-181 - Jae-sun Seo, Ron Ho, Jon K. Lexau, Michael Dayringer, Dennis Sylvester, David T. Blaauw:
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. 182-183 - Sherif T. Eid, Morgan Whately, Sandeep Krishnegowda:
A microcontroller-based PVT control system for a 65nm 72Mb synchronous SRAM. 184-185 - Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy:
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. 186-187 - David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, David T. Blaauw:
In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. 188-189 - Prashant Singh, Zhiyoong Foo, Michael Wieckowski, Scott Hanson, Matthew Fojtik, David T. Blaauw, Dennis Sylvester:
Early detection of oxide breakdown through in situ degradation sensing. 190-191 - Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno:
A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. 192-193
DC-DC Power Conversion
- Ying Wu, Philip K. T. Mok:
A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvement. 196-197 - Eric G. Soenen, Alan Roth, Justin Shi, Martin Kinyua, Justin Gaither, Elizabeth Ortynska:
A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS. 198-199 - Kwang-Chan Lee, Chang-Seok Chae, Gyu-Ha Cho, Gyu-Hyeong Cho:
A PLL-based high-stability single-inductor 6-channel output DC-DC buck converter. 200-201 - Hani H. Ahmad, Bertan Bakkaloglu:
A 300mA 14mV-ripple digitally controlled buck converter using frequency domain ΔΣ ADC and hybrid PWM generator. 202-203 - Chen Zheng, Dongsheng Ma:
A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control. 204-205 - Pengfei Li, Lin Xue, Deepak Bhatia, Rizwan Bashirullah:
Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOS. 206-207 - Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha P. Chandrakasan:
A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS. 208-209 - Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon:
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency. 210-211
Radar, mm-Wave, & Low-Power Transceivers
- Harish Krishnaswamy, Hossein Hashemi:
A 4-channel 4-beam 24-to-26GHz spatio-temporal RAKE radar transceiver in 90nm CMOS for vehicular radar applications. 214-215 - Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang, Jri Lee:
A fully integrated 77GHz FMCW radar system in 65nm CMOS. 216-217 - Alberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd:
A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications. 218-219 - Federico Vecchi, Stefano Bozzola, Massimo Pozzoni, Davide Guermandi, Enrico Temporiti, Matteo Repossi, Ugo Decanis, Andrea Mazzanti, Francesco Svelto:
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators. 220-221 - Xiongchuan Huang, Simonetta Rampu, Xiaoyan Wang, Guido Dolmans, Harmke de Groot:
A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression. 222-223 - Salvatore Drago, Domine M. W. Leenaerts, Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Bram Nauta:
A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes. 224-225 - Marco Crepaldi, Chen Li, Keith Dronson, Jorge R. Fernandes, Peter R. Kinget:
An Ultra-Low-Power interference-robust IR-UWB transceiver chipset using self-synchronizing OOK modulation. 226-227 - Sanghoon Joo, Wu-Hsin Chen, Tae-Young Choi, Mi-Kyung Oh, Joo-Ho Park, Jae-Young Kim, Byunghoo Jung:
A fully integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with digital RRC synthesis. 228-229 - Yuanjin Zheng, Shengxi Diao, Chyuen-Wei Ang, Yuan Gao, Foo Chung Choong, Zhiming Chen, Xin Liu, Yisheng Wang, Xiaojun Yuan, Chun-Huat Heng:
A 0.92/5.3nJ/b UWB impulse radio SoC for communication and localization. 230-231
Emerging Medical Applications
- Chii-Wann Lin, Hung-Wei Chiu, Mu-Lien Lin, Chi-Heng Chang, I-Hsiu Ho, Po Hsiang Fang, Yi Chin Li, Chang Lun Wang, Yao-Chuan Tsai, Yeong-Ray Wen, Win-Pin Shih, Yao-Joe Yang, Shey-Shi Lu:
Pain control on demand based on pulsed radio-frequency stimulation of the dorsal root ganglion using a batteryless implantable CMOS SoC. 234-235 - Eric Y. Chow, Sudipto Chakraborty, William J. Chappell, Pedro P. Irazoqui:
Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implants. 236-237 - Kunal Paralikar, Peng Cong, Wesley Santa, David Dinsmoor, Bob Hocken, Gordon Munns, Jon Giftakis, Timothy Denison:
An implantable 5mW/channel dual-wavelength optogenetic stimulator for therapeutic neuromodulation research. 238-239 - Paolo Livi, Flavio Heer, Urs Frey, Douglas J. Bakkum, Andreas Hierlemann:
Compact voltage and current stimulation buffer for high-density microelectrode arrays. 240-241
Frequency & Clock Synthesis
- Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp:
A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. 244-245 - Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang:
A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. 246-247 - M. Kondou, A. Matsuda, Hiroshi Yamazaki, O. Kobayashi:
A 0.3mm2 90-to-770MHz fractional-N Synthesizer for a digital TV tuner. 248-249 - Shayan Farahvash, William Roberts, Jake Easter, Rachel Wei, David Stegmeir, Li Jin:
A low-noise frequency synthesizer for infrastructure applications. 250-251 - Olivier Richard, Alexandre Siligaris, Franck Badets, Cedric Dehos, Cedric Dufis, Pierre Busson, Pierre Vincent, Didier Belot, Pascal Urard:
A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications. 252-253
Non-Volatile Memory
- David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki:
Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. 256-257 - Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe:
A 64Mb MRAM with clamped-reference and adequate-reference schemes. 258-259 - Christophe J. Chevallier, Chang Hua Siau, Seow Fong Lim, Sri Rama Namala, Misako Matsuoka, Bruce L. Bateman, Darrell Rinerson:
A 0.13µm 64Mb multi-layered conductive metal-oxide memory. 260-261 - Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. 262-263 - Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda:
A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. 264-265