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IEEE Journal of Solid-State Circuits, Volume 39
Volume 39, Number 1, January 2004
- Cheung Fai Lee, Philip K. T. Mok
:
A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique. 3-14 - Francesco Gatta, Danilo Manstretta
, Paolo Rossi, Francesco Svelto:
A fully integrated 0.18-μm CMOS direct conversion receiver front-end with on-chip LO for UMTS. 15-23 - Christian Fager, José Carlos Pedro
, Nuno Borges de Carvalho
, Herbert Zirath, Fernando Fortes
, Maria João Rosário
:
A comprehensive analysis of IMD behavior in RF CMOS power amplifiers. 24-34 - Feng-Jung Huang, Kenneth K. O:
Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p-silicon substrates. 35-41 - In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang:
A CMOS self-regulating VCO with low supply sensitivity. 42-48 - Sudhakar Pamarti
, Lars C. Jansson, Ian Galton:
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. 49-62 - Ruoxin Jiang, Terri S. Fiez:
A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process. 63-74 - Shouli Yan, Edgar Sánchez-Sinencio:
A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth. 75-86 - Seng-Pan U, Rui Paulo Martins, José E. Franca:
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS. 87-99 - Esther Rodríguez-Villegas, Alberto Yúfera
, Adoración Rueda
:
A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion. 100-111 - Sung Min Park, Hoi-Jun Yoo:
1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications. 112-121 - Chris Winstead, Jie Dai, Shuhuan Yu, Chris J. Myers, Reid R. Harrison, Christian Schlegel:
CMOS analog MAP decoder for (8, 4) Hamming code. 122-131 - Sangrok Lee, James C. Morizio
, Kristina M. Johnson:
Novel frame buffer pixel circuits for liquid-crystal-on-silicon microdisplays. 132-139 - Dongsheng Ma, Wing-Hung Ki
, Chi-Ying Tsui
:
An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction. 140-149 - Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Synchronous mirror delay for multiphase locking. 150-156 - José Pineda de Gyvez, Hans Tuinhout:
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits. 157-168 - Yuan-Hao Huang, Hsi-Pin Ma, Ming-Luen Liou, Tzi-Dar Chiueh:
A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications. 169-183 - Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu:
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. 184-193 - Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara:
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. 194-206 - Koichi Murata, Kimikazu Sano, Hiroto Kitabayashi, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki:
100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology. 207-213 - Kostas Karadamoglou, Nikolaos P. Paschalidis, Emmanuel Sarris, Nikos Stamatopoulos, George Kottaras, Vassilis Paschalidis:
An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments. 214-222 - Tae Wook Kim, Bonkee Kim, Kwyro Lee:
Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors. 223-229 - Yalcin Alper Eken, John P. Uyemura:
A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS. 230-233 - Wei-Zen Chen, Jia-Xian Chang, Ying-Jen Hong, Meng-Tzer Wong, Chien-Liang Kuo:
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process. 234-237 - Farhang Vessal, C. André T. Salama:
An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology. 238-241 - Anna Richelli
, Luigi Colalongo, Michele Quarantelli, M. Carmina, Zsolt Miklós Kovács-Vajna:
A fully integrated inductor-based 1.8-6-V step-up converter. 242-245 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding. 246-251 - J. Doyle, Young Jun Lee, Yong-Bin Kim, H. Wilsch, Fabrizio Lombardi:
A CMOS subbandgap reference circuit with 1-v power supply voltage. 252-255 - Esther Rodríguez-Villegas, Alberto Yúfera
, Adoración Rueda
:
A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion. 256-259 - Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Design of ESD power protection with diode structures for mixed-power supply systems. 260-264 - Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa:
A dynamically reconfigurable SIMD processor for a vision chip. 265-268
Volume 39, Number 2, February 2004
- Bernhard Boser:
New Associate Editors. 274 - Federico Bruccoleri, Eric A. M. Klumperink, Bram Nauta
:
Wide-band CMOS low-noise amplifier exploiting thermal noise canceling. 275-282 - Mostafa A. I. Elmala, Sherif H. K. Embabi:
Calibration of phase and gain mismatches in Weaver image-reject receiver. 283-289 - Angelika Schneider, Oliver Werther:
Nonlinear analysis of noise in current-steering variable gain amplifiers. 290-296 - Yorgos Palaskas, Yannis P. Tsividis, Vladimir I. Prodanov, Vito Boccuzzi:
A "divide and conquer" technique for implementing wide dynamic range continuous-time filters. 297-307 - Ji-Jon Sit
, Rahul Sarpeshkar:
A micropower logarithmic A/D with offset and temperature compensation. 308-319 - Ralf Wunderlich, Carsten Thomas, Klaus Schumacher:
A monolithic positioning system. 320-326 - Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang:
The CMOS carry-forward adders. 327-336 - Rajeevan Amirtharajah
, Anantha P. Chandrakasan:
A micropower programmable DSP using approximate signal processing based on distributed arithmetic. 337-347 - Jongsun Park
, Woopyo Jeong, Hamid Mahmoodi-Meimand
, Yongtao Wang, Hunsoo Choo, Kaushik Roy:
Computation sharing programmable FIR filter for low-power and high-performance applications. 348-357 - Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo:
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. 358-367 - Xiang Guan, Ali Hajimiri
:
A 24-GHz CMOS front-end. 368-373 - Willy Hioe, Kenji Maio, Takashi Oshima
, Yoshiyuki Shibahara, Takeshi Doi, Kiyoharu Ozaki, Satoshi Arayashiki:
0.18-μm CMOS Bluetooth analog receiver with -88-dBm sensitivity. 374-377 - Stefano Pellerano, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. 378-383 - Federico Baronti
, Diego Lunardini, Roberto Roncella
, Roberto Saletti
:
A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme. 384-387 - Rajamohana Hegde, Naresh R. Shanbhag:
A voltage overscaled low-power digital filter IC. 388-391
Volume 39, Number 3, March 2004
- Bernhard Boser:
New Associate Editor. 410 - Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten:
A double-sampling extended-counting ADC. 411-418 - Jong-Sang Choi, Moon-Sang Hwang, Deog-Kyoon Jeong:
A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method. 419-425 - Alexandru A. Ciubotaru
, Javier S. Garcia:
An integrated direct-coupled 10-Gb/s driver for common-cathode VCSELs. 426-433 - Jaime Ramírez-Angulo, Antonio J. López-Martín
, Ramón González Carvajal
, Fernando Muñoz Chavero
:
Very low-voltage analog signal processing based on quasi-floating gate transistors. 434-442 - George Patounakis, Yee William Li, Kenneth L. Shepard:
A fully integrated on-chip DC-DC conversion and power management system. 443-451 - Zhinian Shu, Ka Lok Lee, Bosco H. Leung:
A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture. 452-462 - Sung-Rung Han, Shen-Iuan Liu:
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle. 463-468 - Ching-Che Chung
, Chen-Yi Lee:
A new DLL-based approach for all-digital multiphase clock generation. 469-475 - Liming Xiu, Wen Li, J. Meiners, R. Padakanti:
A novel all-digital PLL with software adaptive filter. 476-483 - Koushik Maharatna
, Eckhard Grass, Ulrich Jagdhold:
A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM. 484-493 - Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolic
:
A shared-well dual-supply-voltage 64-bit ALU. 494-500 - Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan:
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. 501-510 - Josep Rius Vázquez, José Pineda de Gyvez:
Built-in current sensor for ΔIDDQ testing. 511-518 - Chung-Yu Wu, Chung-Yun Chou:
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator. 519-521 - Frank Ellinger:
26-42 GHz SOI CMOS low noise amplifier. 522-528 - Kamran Farzan, David A. Johns:
A CMOS 10-gb/s power-efficient 4-PAM transmitter. 529-532 - Stephen Docking, Manoj Sachdev:
An analytical equation for the oscillation frequency of high-frequency ring oscillators. 533-537 - Viktor Gruev, Ralph Etienne-Cummings:
A pipelined temporal difference imager. 538-543
Volume 39, Number 4, April 2004
- Yoshinobu Nakagome, Bruce Gieseke:
Introduction to the Special Issue. 547-548 - Asad A. Abidi:
RF CMOS comes of age. 549-561 - Takahide Kadoyama, Norihito Suzuki, Noboru Sasho, Hiroshi Iizuka, Ikuho Nagase, Hideaki Usukubo, Masayuki Katakura:
A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-μm CMOS. 562-568 - Mamoru Ugajin, Akihiro Yamagishi, Junichi Kodate, Mitsuru Harada, Tsuneo Tsukahara:
Macromodels in the frequency domain analysis of microwave resonators. 569-576 - Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Eiji Taniguchi, Hiro-omi Ueda, Noriharu Suematsu, Tatsuo Oomori:
21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs). 577-584 - David B. Barkin, Andrew C. Y. Lin, David K. Su, Bruce A. Wooley:
A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering. 585-593 - Jri Lee, Behzad Razavi:
A 40-GHz frequency divider in 0.18-μm CMOS technology. 594-601 - Jackie Koon Lun Wong, Hamid Hatamkhani, Mozhgan Mansuri, Chih-Kong Ken Yang:
A 27-mW 3.6-gb/s I/O transceiver. 602-612 - Yoshio Miki, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, Masahito Sonehara:
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking. 613-621 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution. 622-628 - Ingo Hehemann, Werner Brockherde
, Holger Hofmann, Armin Kemna, Bedrich J. Hosticka:
A single-chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems. 629-635 - Simon Tam, Rahul Dilip Limaye, Utpal Nagarji Desai:
Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache. 636-642 - Eiichi Takahashi, Yuji Kasai
, Masahiro Murakawa
, Tetsuya Higuchi:
Post-fabrication clock-timing adjustment using genetic algorithms. 643-650 - Ali Muhtaroglu
, Greg Taylor, Tawfik Rahal-Arabi:
On-die droop detector for analog sensing of power supply noise. 651-660 - Mitsuru Hiraki, Kenichi Fukui, Takayasu Ito:
A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme. 661-666 - Hugh P. McAdams, Randy Acklin, Terry Blake, Xiao-Hong Du, Jarrod Eliason, John Y. Fong, William F. Kraus, David Liu, Sudhir Madan, Ted Moise, Sreedhar Natarajan, Ning Qian, Yunchen Qiu, Keith Remack, J. Rodriguez, John Roscher, Anand Seshadri, Scott R. Summerfelt:
A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process. 667-677 - John K. DeBrosse, Dietmar Gogl, Alexander Bette, Heinz Hoenigschmid, Raphael Robertazzi, Christian Arndt, Daniel Braun, D. Casarotto, Robert Havreluk, Stefan Lammers, Werner Obermaier, William R. Reohr, Hans Viehmann, William J. Gallagher, Gerhard Müller:
A high-speed 128-kb MRAM core for future universal memory applications. 678-683 - Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade:
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. 684-693 - Jae-Yoon Sim, Kee-Won Kwon, Ki-Chul Chun:
Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs. 694-703 - Yee William Li, George Patounakis, Kenneth L. Shepard, Steven M. Nowick:
High-throughput asynchronous datapath with software-controlled voltage scaling. 704-708 - Shwetabh Verma, Junfeng Xu, Thomas H. Lee:
A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis. 709-713 - Raymond Montemayor:
A 410-mW 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable applications. 714-718
Volume 39, Number 5, May 2004
- Jiangfeng Wu, Gary K. Fedder
, L. Richard Carley:
A low-noise low-offset capacitive sensing amplifier for a 50-μg√Hz monolithic CMOS MEMS accelerometer. 722-730 - SeongHwan Cho, Anantha P. Chadrakasan:
A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications. 731-739 - Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino:
PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. 740-750 - Thomas Olsson, Peter Nilsson:
A digitally controlled PLL for SoC applications. 751-760 - Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu:
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. 761-774 - Salvatore Levantino
, Luca Romanò, Stefano Pellerano, Carlo Samori
, Andrea L. Lacaita
:
Phase noise in digital frequency dividers. 775-784 - Hsi-Pin Ma, Ming-Luen Liou, Tzi-Dar Chiueh:
A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability. 785-794 - Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong:
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. 795-803 - Kenichiro Anjo, Atsushi Okamura, Masato Motomura
:
Wrapper-based bus implementation techniques for performance improvement and cost reduction. 804-817 - Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan:
A leakage reduction methodology for distributed MTCMOS. 818-826 - Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara
:
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. 827-833 - Ming-Huang Liu, Kuo-Chan Huang, Wei-Yang Ou, Tsung-Yi Su, Shen-Iuan Liu:
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC. 834-836 - Koon-Lun Jackie Wong, Chih-Kong Ken Yang:
Offset compensation in comparators with minimum input-referred supply noise. 837-840 - Neric H. W. Fong, Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Garry Tarr:
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology. 841-846 - Yongchul Song, Beomsup Kim:
A 14-b direct digital frequency synthesizer with sigma-delta noise shaping. 847-851 - Chi-Fang Li, Yuan-Sun Chu, Wern-Ho Sheen, Fu-Chin Tian, Jan-Shin Ho:
A low-power ASIC design for cell search in the W-CDMA system. 852-857
Volume 39, Number 6, June 2004
- Bernhard Boser:
New Associate Editor. 862 - Niranjan A. Talwalkar, C. Patrick Yue
, Haitao Gan, S. Simon Wong:
Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications. 863-870 - Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu:
Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver. 871-884 - Christian Kromer, Gion Sialm, Thomas Morf, Martin L. Schmatz, Frank Ellinger, Daniel Erni, Heinz Jäckel:
A low-power 20-GHz 52-dBΩ transimpedance amplifier in 80-nm CMOS. 885-894 - Tom Zimmerman, James R. Hoff:
The design of a charge-integrating modified floating-point ADC chip. 895-905 - Yi-Ming Wang, Jinn-Shyan Wang:
A low-power half-delay-line fast skew-compensation circuit. 906-918 - Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu:
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. 919-926 - Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai:
90% write power-saving SRAM using sense-amplifying memory cell. 927-933 - Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi:
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. 934-940 - Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-Jin Lee, Chang-Hyun Kim:
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. 941-951 - Hye-Ryoung Kim, Choong-Yul Cha, Seung-Min Oh, Moon-Su Yang, Sang-Gug Lee:
A very low-power quadrature VCO with back-gate coupling. 952-955 - Qiurong He, Milton Feng:
Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier. 956-959 - Paolo Cusinato:
Gain/bandwidth programm