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ORCIDOliver Chiu-sing Choy
Oliver C. S. Choy – Chiu-sing Choy – Chiu-Sing Choy
2020 – today
- 2023
[c77]Jinfa Hong, Hei Wong
, Oliver C. S. Choy, Ray C. C. Cheung:
A Platform for Adaptive Interference Mitigation and Intent Analysis Using OpenLANE. ICSPCC 2023: 1-6- 2020
- [j38]Huan Wu, Hongda Wang, Chester Shu, Chiu-Sing Choy, Chao Lu:
BOTDA Fiber Sensor System Based on FPGA Accelerated Support Vector Regression. IEEE Trans. Instrum. Meas. 69(6): 3826-3837 (2020)
2010 – 2019
- 2019
- [j37]Weiwei Shi, Yuan Xu, Chiu-Sing Choy, Zhiyong Chen, Junwei Yang, Robert K. F. Teng, Mei Jiang, X. Deng:
A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1733-1737 (2019) - [c76]Huan Wu, Hongda Wang, Chester Shu, Chiu-Sing Choy, Chao Lu:
Brillouin Optical Time Domain Analyzer Fiber Sensor Based on FPGA Accelerated Support Vector Regression. OFC 2019: 1-3 - 2018
- [j36]Hongda Wang, Weiwei Shi, Chiu-Sing Choy:
Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM. IEEE Access 6: 67277-67290 (2018) - [j35]Weiwei Shi, An Pan, Shi Yu, Chiu-sing Choy:
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 159-167 (2018) - [j34]Weiwei Shi, Hai-Peng Wang, Chiu-Sing Choy, Junwei Yang, Mei Jiang, Robert K. F. Teng, Mingcheng Zhu:
A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1430-1434 (2018) - [c75]Zhou Fang, Howan Leung, Chiu-sing Choy:
Spatial temporal GRU convnets for vision-based real time epileptic seizure detection. ISBI 2018: 1026-1029 - 2017
- [c74]Hongda Wang, Weiwei Shi, Chiu-sing Choy:
Integrating channel selection and feature selection in a real time epileptic seizure detection system. EMBC 2017: 3206-3211 - 2016
- [j33]Hao Wang, Xian Tang, Oliver Chiu-sing Choy, Gerald E. Sobelman:
Cascaded Network Body Channel Model for Intrabody Communication. IEEE J. Biomed. Health Informatics 20(4): 1044-1052 (2016) - [c73]Hongda Wang, Chiu-sing Choy:
Automatic seizure detection using correlation integral with nonlinear adaptive denoising and Kalman filter. EMBC 2016: 1002-1005 - [c72]Weiwei Shi, Zhao Guangdong, Oliver Chiu-sing Choy:
Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells. ISVLSI 2016: 182-187 - [c71]Lie Xu, Chiu-sing Choy, Yi-Wen Li:
Deep sparse rectifier neural networks for speech denoising. IWAENC 2016: 1-5 - [c70]Weiwei Shi, Chiu-sing Choy:
A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption. SoCC 2016: 125-128 - 2015
- [j32]Hao Wang, Xian Tang, Chiu-sing Choy, Ka Nang Leung, Kong-Pang Pun:
A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2829-2841 (2015) - [c69]Weiwei Shi, Linqing Fu, Chiu-sing Choy:
Subthreshold passive RFID tag's baseband processor core design with custom modules and cells. ICECS 2015: 45-48 - 2014
- [c68]Jianfeng Wang, Chiu-sing Choy, Tak Lon Chao, Ko-Chun Kit, Kong-Pang Pun, Wanli Ouyang, Xiao-Gang Wang:
Simplifying HOG arithmetic for speedy hardware realization. APCCAS 2014: 61-64 - [c67]Weiwei Shi, Oliver Chiu-sing Choy:
Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells. ICECS 2014: 447-450 - [c66]Ho Chuen Jackson Yeung, Evangeline F. Y. Young, Chiu-sing Choy:
Reducing pin count on cross-referencing Digital Microfluidic Biochip. ISCAS 2014: 790-793 - [c65]Hao Wang, Jianfeng Wang, Chiu-Sing Choy:
A 2.5-Mbps, 170-cm transmission distance IntraBody communication receiver front end design and its synchronization technique research. MWSCAS 2014: 643-646 - [c64]Hao Wang, Chiu-Sing Choy:
A novel high speed, low power IntraBody Communication Receiver Front End based on sampling rate boosting switched-capacitor filter. MWSCAS 2014: 872-875 - [c63]Weiwei Shi, Oliver Chiu-sing Choy:
A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below. SoCC 2014: 54-57 - 2013
- [j31]S. Man Ho Ho, Yanqing Ai, Thomas Chun-Pong Chau, Steve C. L. Yuen, Oliver Chiu-sing Choy, Philip Heng Wai Leong, Kong-Pang Pun:
Architecture and Design Flow for a Highly Efficient Structured ASIC. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 424-433 (2013) - [c62]Yanqing Ai, Oliver Chiu-sing Choy:
The Impact of Nodes Embedded with Data Processing Unit on Energy Consumption in a Wireless BAN. ANT/SEIT 2013: 938-943 - [c61]Weiwei Shi, Oliver Chiu-sing Choy, Robert K. F. Teng:
Key component designs of subthreshold baseband processors in passive RF device. ASICON 2013: 1-4 - [c60]Yanqing Ai, Chiu-Sing Choy:
A data compression based power aware BAN system exploration of IEEE 802.15.6. ISCE 2013: 177-178 - 2012
- [j30]Wen Fan, Oliver Chiu-sing Choy:
Robust, Low-Complexity, and Energy Efficient Downlink Baseband Receiver Design for MB-OFDM UWB System. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 399-408 (2012) - [j29]Ke Xu, Min Zhang, Chiu-sing Choy:
Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels - A Showcase. J. Signal Process. Syst. 67(3): 317-330 (2012) - [c59]Weiwei Shi, Oliver Chiu-sing Choy:
A process-compatible passive RFID tag's digital design for subthreshold operation. ICECS 2012: 528-531 - [e2]Oliver C. S. Choy, Ray C. C. Cheung, Peter M. Athanas, Kentaro Sano:
Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings. Lecture Notes in Computer Science 7199, Springer 2012, ISBN 978-3-642-28364-2 [contents] - [e1]Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy:
VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers. IFIP Advances in Information and Communication Technology 379, Springer 2012, ISBN 978-3-642-32769-8 [contents] - 2011
- [c58]Wen Fan, Oliver Chiu-sing Choy:
Robust and efficient baseband receiver design for MB-OFDM UWB system. ASP-DAC 2011: 111-112 - 2010
- [j28]Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun, Lincoln Lai Kan Leung, Jianping Guo, Yuen Sum Ng, Chi Fat Chan, Weiwei Shi, Yang Hong, Marco Ho, Ki-Leung Mak, Yanqing Ai:
RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology. J. Low Power Electron. 6(1): 141-149 (2010) - [j27]Chi Fat Chan, Kong-Pang Pun, Ka Nang Leung, Jianping Guo, Lincoln Lai Kan Leung, Oliver Chiu-sing Choy:
A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders. IEEE J. Solid State Circuits 45(3): 587-599 (2010) - [j26]Ke Xu, Tsu-Ming Liu, Jiun-In Guo, Oliver Chiu-sing Choy:
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding. J. Signal Process. Syst. 60(1): 131-145 (2010) - [c57]Pui-wai Chan, Chiu-sing Choy:
Performance evaluation of OFDM de-modulator with various multiplier architectures for UWB system. APCCAS 2010: 418-421 - [c56]Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy:
Rapid prototyping on a structured ASIC fabric. ASP-DAC 2010: 379-380 - [c55]Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong:
Design of a single layer programmable Structured ASIC library. DDECS 2010: 32-35 - [c54]Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong, Oliver C. S. Choy, Kong-Pang Pun:
Structured ASIC: Methodology and comparison. FPT 2010: 377-380 - [c53]Ling Xin, Chiu-sing Choy:
A low-latency NoC router with lookahead bypass. ISCAS 2010: 3981-3984
2000 – 2009
- 2009
- [j25]Ke Xu, Oliver Chiu-sing Choy:
Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding. EURASIP J. Embed. Syst. 2009 (2009) - [j24]Min Zhang, Oliver Chiu-sing Choy:
Low-Cost Allocator Implementations for Networks-on-Chip Routers. VLSI Design 2009: 415646:1-415646:10 (2009) - [c52]Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang:
A comparison of via-programmable gate array logic cell circuits. FPGA 2009: 53-62 - [c51]Wen Fan, Oliver Chiu-sing Choy, Ka Nang Leung:
Robust and Low Complexity Packet Detector Design for MB-OFDM UWB. ISCAS 2009: 693-696 - [c50]Bing Li, Cheong-Fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy:
A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators. ISCAS 2009: 1545-1548 - [c49]Chi Fat Chan, Weiwei Shi, Kong-Pang Pun, Lincoln Lai Kan Leung, Ka Nang Leung, Oliver Chiu-sing Choy:
A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders. ISCAS 2009: 1581-1584 - 2008
- [j23]Siu-Kei Tang, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-Fat Chan, Ka Nang Leung:
A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 653-657 (2008) - [j22]Ke Xu, Chiu-sing Choy:
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC. IEEE Trans. Circuits Syst. Video Technol. 18(3): 363-374 (2008) - [j21]Ke Xu, Oliver Chiu-sing Choy:
A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 302-313 (2008) - [c48]Misteltein Pak-Kee Chan, Oliver Chiu-sing Choy, Kong-Pang Pun, Cheong-Fat Chan, Alex Ka Nang Leung:
Enhanced channel selection using digital low-IF in Weaver receiver architecture. APCCAS 2008: 33-36 - [c47]Yang Hong, Chi Fat Chan, Jianping Guo, Yuen Sum Ng, Weiwei Shi, Lincoln Lai Kan Leung, Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun:
Design of passive UHF RFID tag in 130nm CMOS technology. APCCAS 2008: 1371-1374 - [c46]Min Zhang, Chiu-sing Choy:
Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip. NOCS 2008: 207-208 - 2007
- [j20]Ke Xu, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Priority-Based Heading One Detector in H.264/AVC Decoding. EURASIP J. Embed. Syst. 2007 (2007) - [j19]Ke Xu, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing. IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 984-988 (2007) - [j18]Wei Han, Kwok-Wai Hon, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. J. VLSI Signal Process. 47(3): 223-232 (2007) - [c45]Ke Xu, Chiu-sing Choy:
Low-power H.264/AVC baseline decoder for portable applications. ISLPED 2007: 256-261 - 2006
- [j17]Kong-Pang Pun, Wang Tung Cheng, Chiu-Sing Choy, Cheong-Fat Chan:
A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator. IEEE J. Solid State Circuits 41(6): 1353-1363 (2006) - [c44]Wang-Chi Cheng, Cheong-Fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy:
Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. APCCAS 2006: 195-198 - [c43]King-Keung Mok, Ka-Hung Tsang, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
Adiabatic Smart Card. APCCAS 2006: 287-290 - [c42]Wang-Chi Cheng, Cheong-Fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy:
0.8 V GPS band CMOS VCO with 29% Tuning Range. APCCAS 2006: 522-525 - [c41]Chi-Hong Chan, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm. ISCAS 2006 - [c40]Wei Han, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
An efficient MFCC extraction method in speech recognition. ISCAS 2006 - [c39]Xiao-Yong He, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-Fat Chan:
A 0.5V fully differential OTA with local common feedback. ISCAS 2006 - [c38]Pak-Keung Leung, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application. ISCAS 2006 - [c37]Siu-Kei Tang, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-Fat Chan:
A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications. ISCAS 2006 - [c36]Alex K. Y. Wong, Kong-Pang Pun, Yuan-Ting Zhang, Oliver Chiu-sing Choy:
An ECG measurement IC using driven-right-leg circuit. ISCAS 2006 - [c35]Ke Xu, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder. ISCAS 2006 - 2005
- [c34]Wang Tung Cheng, Kong-Pang Pun, Chiu-Sing Choy, Cheong-Fat Chan:
A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator. ESSCIRC 2005: 455-458 - [c33]Pui-Tak So, Cheong-Fat Chan, Chiu-sing Choy, Kong-Pang Pun:
Ramp voltage supply using adiabatic charging principle. ISCAS (3) 2005: 2152-2155 - [c32]Nang-Ching Yeung, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-Fat Chan:
Active RC filter with reduced capacitance by current division technique. ISCAS (4) 2005: 3279-3282 - [c31]Chi-Leung San, Chiu-sing Choy, Pak-Kee Chan, Cheong-Fat Chan, Kong-Pang Pun:
Realization of card-centric framework: a card-centric computer [smart cards]. ISCAS (5) 2005: 4999-5002 - [c30]Wei Han, Cheong-Fat Chan, Chiu-sing Choy, Kong-Pang Pun:
A speech recognizer with selectable model parameters. ISCAS (6) 2005: 5842-5845 - 2004
- [j16]Jing-Ling Yang, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
A high-efficiency strongly self-checking asynchronous datapath. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1484-1494 (2004) - [j15]Ragnarok Pak-Kee Chan, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
A low-latency asynchronous shift register. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 217-221 (2004) - [j14]Kong-Pang Pun, Chiu-sing Choy, Cheong-Fat Chan, José Epifânio da Franca:
An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 254-256 (2004) - [j13]Pak-Kee Chan, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Preparing smartcard for the future: from passive to active. IEEE Trans. Consumer Electron. 50(1): 245-250 (2004) - [j12]Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy:
High Speed Curve Interpolating D/A Converter. J. VLSI Signal Process. 38(1): 5-11 (2004) - [c29]Chun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-Fat Chan, Kong-Pang Pun:
A low power asynchronous Java processor for contactless smart card. ASP-DAC 2004: 553-554 - [c28]Pak-Kee Chan, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Card-Centric Framework - Providing I/O Resources for Smart Cards. CARDIS 2004: 225-240 - [c27]Junhua Shen, Kong-Pang Pun, Chiu-sing Choy, Cheong-Fat Chan:
An IF input continuous-time sigma-delta analog-digital converter with high image rejection. ICECS 2004: 101-104 - [c26]Wing-Kin Chan, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
An asynchronous SOVA decoder for wireless communication application. ISCAS (2) 2004: 517-520 - [c25]Wang Tung Cheng, Kong-Pang Pun, Cheong-Fat Chan, Chiu-sing Choy:
An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing. ISCAS (1) 2004: 1140-1143 - [c24]Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Pipelines in Dynamic Dual-Rail Circuits. PATMOS 2004: 701-710 - 2003
- [j11]Kin-Pui Ho, Cheong-Fat Chan, Chiu-Sing Choy, Kong-Pang Pun:
Reversed nested Miller compensation with voltage buffer and nulling resistor. IEEE J. Solid State Circuits 38(10): 1735-1738 (2003) - [c23]Pui-Lam Siu, Chiu-Sing Choy, Chi Fat Chan, Kong-Pang Pun:
A contactless smartcard designed with asynchronous circuit technique. ESSCIRC 2003: 213-216 - [c22]W. K. Yeung, Cheong-Fat Chan, Chiu-sing Choy, Kong-Pang Pun:
Clock recovery circuit with adiabatic technology (quasi-static CMOS logic). ISCAS (2) 2003: 185-187 - [c21]Pak-Keung Leung, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor. ISCAS (5) 2003: 337-340 - [c20]Wei Han, Kwok-Wai Hon, Cheong-Fat Chan, Tan Lee, Chiu-sing Choy, Kong-Pang Pun, Pak-Chung Ching:
An HMM-based speech recognition IC. ISCAS (2) 2003: 744-747 - [c19]Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
Design for Self-Checking and Self-Timed Datapath. VTS 2003: 417-430 - 2002
- [c18]Wang-Chi Cheng, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
A 900 MHz 1.2 V CMOS mixer with high linearity. APCCAS (1) 2002: 1-4 - [c17]Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
A Totally Self-Checking Dynamic Asynchronous Datapath. Asian Test Symposium 2002: 27-32 - [c16]Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy:
A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter. ISCAS (3) 2002: 137-140 - [c15]Kong-Pang Pun, Chiu-sing Choy, Cheong-Fat Chan, José E. Franca:
A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators. ISCAS (4) 2002: 221-224 - [c14]Wang-Chi Cheng, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
A 1.2 V 900 MHz CMOS mixer. ISCAS (5) 2002: 365-368 - [c13]Kin-Pui Ho, Cheong-Fat Chan, Chiu-sing Choy, Kong-Pang Pun:
A CMOS current feedback operational amplifier with active current mode compensation. ISCAS (1) 2002: 709-712 - 2001
- [j10]Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan:
A self-timed divider using a new fast and robust pipeline scheme. IEEE J. Solid State Circuits 36(6): 917-923 (2001) - [j9]Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan:
Asynchronous cross-pipelined multiplier. IEEE J. Solid State Circuits 36(8): 1272-1275 (2001) - [j8]Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan:
A New Control Circuit for Asynchronous Micropipelines. IEEE Trans. Computers 50(9): 992-997 (2001) - [c12]Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
A low power asynchronous DES. ISCAS (4) 2001: 538-541 - [c11]Lai-Kan Leung, Cheong-Fat Chan, Oliver Chiu-sing Choy:
A giga-hertz CMOS digital controlled oscillator. ISCAS (4) 2001: 610-613 - [c10]Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. ISCAS (4) 2001: 910-913 - 2000
- [j7]Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy:
CMOS high speed interpolators based on parallel architecture. IEEE Trans. Consumer Electron. 46(2): 326-329 (2000) - [j6]Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy:
High speed CMOS digital-to-analog converter with linear interpolator. IEEE Trans. Consumer Electron. 46(4): 1137-1142 (2000) - [c9]Tin-Y. Tang, Chiu-sing Choy, Pui-Lam Siu, Cheong-Fat Chan:
Design of self-timed asynchronous Booth's multiplier. ASP-DAC 2000: 15-16 - [c8]Tin-Yau Tang, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
An ALU design using a novel asynchronous pipeline architecture. ISCAS 2000: 361-364 - [c7]Wing-Sum Mak, Cheong-Fat Chan, Ka-Wai Cheung, Chiu-Sing Choy:
An 8×8 adiabatic quasi-static CMOS multiplier. ISCAS 2000: 553-556
1990 – 1999
- 1999
- [j5]Vincent Wing-Yun Sit, Chiu-Sing Choy, Cheong-Fat Chan:
A four-phase handshaking asynchronous static RAM design for self-timed systems. IEEE J. Solid State Circuits 34(1): 90-96 (1999) - [j4]Tin-Chak Johnson Pang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Wai-kuen Cham:
A self-timed ICT chip for image coding. IEEE Trans. Circuits Syst. Video Technol. 9(6): 856-860 (1999) - [c6]Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-Fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-Ling Yang, Tin-yan Tang:
Pipelined Dataflow Architecture of a Small Processor. PDPTA 1999: 1217-1223 - 1998
- [c5]Oliver Chiu-sing Choy, Tin-Chak Johnson Pang, Juraj Povazanec, Cheong-Fat Chan:
A Useful Micropipeline Architecture to Implement DSP Algorithms. EUROMICRO 1998: 10212- - [c4]Juraj Povazanec, Chiu-Sing Choy, Cheong-Fat Chan:
Asynchronous logic in bit-serial arithmetic. ICECS 1998: 175-178 - 1997
- [j3]Chiu-Sing Choy, M. H. Ku, Chi Fat Chan:
A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. IEEE J. Solid State Circuits 32(6): 913-917 (1997) - [c3]Tin-Chak Johnson Pang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Wai-kuen Cham:
Self-timed 1-D ICT processor. ASP-DAC 1997: 669-670 - 1996
- [j2]Oliver Chiu-sing Choy, Lap-kong Chan, Ray Chan, Cheong-Fat Chan:
Test Generation with Dynamic Probe Points in High Observability Testing Environment. IEEE Trans. Computers 45(1): 88-96 (1996) - [j1]Chiu-sing Choy, Tsz-Shing Cheung, Kam-Keung Wong:
Incremental layout placement modification algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4): 437-445 (1996) - 1995
- [c2]Chiu-sing Choy, Cheong-Fat Chan, M. H. Ku:
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver. ISCAS 1995: 307-310 - 1994
- [c1]W. Y. Lo, Chiu-sing Choy, Cheong-Fat Chan:
Hardware emulation board based on FPGAs and programmable interconnections. RSP 1994: 126-130
Coauthor Index
[c50] [j23] [c48] [j20] [j19] [j18] [j17] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c35] [c34] [c33] [c32] [c31] [c30] [j16] [j15] [j14] [j13] [j12] [c29] [c28] [c27] [c26] [c25] [c24] [j11] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j10] [j9] [j8] [c12] [c11] [c10] [j7] [j6] [c9] [c8] [c7] [j5] [j4] [c6] [c5] [c4] [c3] [j2] [c2] [c1]
[j32] [c68] [j31] [j28] [j27] [c56] [c55] [c54] [c52] [c50] [c49] [j23] [c48] [c47] [j20] [j19] [j18] [j17] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j16] [j15] [j14] [j13] [c29] [c28] [c27] [c26] [c25] [c24] [j11] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c15] [c14] [c13]
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-02-08 00:51 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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the dblp computer science bibliography is funded and supported by:
