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Journal Articles
- 2025
[j19]Feng Bu, Ruixue Ding, Depeng Sun, Yuan Gao, Ruiqing Wang, Xiaoteng Zhao, Rong Zhou, Shubin Liu:
A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur. Microelectron. J. 155: 106483 (2025)- [j18]Zekai Yang, Xiaoteng Zhao
, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu:
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator. Microelectron. J. 166: 106870 (2025) - [j17]Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu:
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator. Microelectron. J. 166: 106872 (2025) - [j16]Miao Zhang, Ruidong Li, Xiaoteng Zhao, Xianting Su, Zhicheng Dong, Zekai Yang, Hongyu Su, Hongzhi Liang, Yukui Yu, Shubin Liu:
Load-driven inductive peaking design for broad band continuous-time linear equalizer. Microelectron. J. 166: 106873 (2025) - [j15]Jie Liu, Xianting Su, Zekai Yang, Zhicheng Dong, Chenxi Han, Xiaoteng Zhao, Shubin Liu:
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units. Microelectron. J. 166: 106874 (2025) - [j14]Yuan Gao, Depeng Sun, Chao Gu, Feng Bu, Bowen Wang, Rong Zhou, Zhicheng Dong, Xiaoteng Zhao, Tao Zhang, Ruixue Ding, Shubin Liu, Zhangming Zhu:
A Low-Noise Class-F23 VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 72(11): 6679-6690 (2025) - [j13]Feng Bu, Ruixue Ding, Depeng Sun, Ge Wang, Yuan Gao, Rong Zhou, Xiaoteng Zhao, Lisheng Chen, Shubin Liu, Zhangming Zhu:
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration. IEEE Trans. Very Large Scale Integr. Syst. 33(5): 1442-1446 (2025) - 2024
- [j12]Shubin Liu, Chenxi Han, Xiaoteng Zhao, Yuhao Zhang, Shixin Li, Hongzhi Liang, Lihong Yang, Zhangming Zhu:
A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS. Sci. China Inf. Sci. 67(8) (2024) - [j11]Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Xianting Su, Hongzhi Liang, Menghao Wang, Zhangming Zhu:
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor. IEEE J. Solid State Circuits 59(11): 3767-3779 (2024) - [j10]Rong Zhou, Jianhang Yang, Linwei Wang, Xiaoteng Zhao, Shubin Liu, Depeng Sun:
A wideband low power RF Receiver Front-End for Internet-of-Things applications. Microelectron. J. 144: 106064 (2024) - [j9]Rong Zhou, Linwei Wang, Jianhang Yang, Zhen Li, Xiaoteng Zhao, Shubin Liu:
A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications. Microelectron. J. 144: 106090 (2024) - [j8]Depeng Sun, Ruiqing Wang, Feng Bu, Yuan Gao, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Rong Zhou:
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators. Microelectron. J. 146: 106140 (2024) - [j7]Depeng Sun, Linguo Huang, Rong Zhou, Feng Bu, Lisheng Chen, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Zhangming Zhu:
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and -250.8-dB FOMPLL. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1909-1913 (2024) - 2023
- [j6]Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2637-2650 (2023) - 2022
- [j5]Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. IEEE J. Solid State Circuits 57(2): 546-561 (2022) - [j4]Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. IEEE J. Solid State Circuits 57(5): 1358-1371 (2022) - 2021
- [j3]Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 89-102 (2021) - 2019
- [j2]Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3330-3339 (2019) - [j1]Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins:
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2223-2236 (2019)
Conference and Workshop Papers
- 2025
- [c9]Chenxi Han, Xiaoteng Zhao, Qi Zhang, Yuan Liu, Yuhao Zhang, Hongzhi Liang, Yukui Yu, Shubin Liu, Zhangming Zhu:
A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS. CICC 2025: 1-3 - [c8]Xiaoteng Zhao, Yuhao Zhang, Hao Chang, Yilong Dong, Chenxi Han, Zekai Yang, Zhicheng Dong, Rong Zhou, Shubin Liu, Zhangming Zhu:
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed. ISSCC 2025: 150-152 - 2024
- [c7]Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Rong Zhou, Depeng Sun, Yong Chen, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. A-SSCC 2024: 1-3 - [c6]Miao Zhang, Xianting Su, Zekai Yang, Zhicheng Dong, Weitan Huang, Menghao Wang, Yukui Yu, Xiaoteng Zhao, Shubin Liu, Zhangming Zhu:
A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers. ICTA 2024: 172-173 - [c5]Zhicheng Dong, Xiaoteng Zhao, Weitan Huang, Yuan Gao, Depeng Sun, Shubin Liu, Lihong Yang, Zhangming Zhu:
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area. ISCAS 2024: 1-5 - 2023
- [c4]Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu:
A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. CICC 2023: 1-2 - 2022
- [c3]Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. ICECS 2022 2022: 1-4 - 2020
- [c2]Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. CICC 2020: 1-4 - 2019
- [c1]Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. APCCAS 2019: 229-232
Coauthor Index
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