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Seokin Hong
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2020 – today
- 2024
- [j11]Sangun Choi
, Seongjun Park, Jaeyong Park, Jongmin Kim, Gunjae Koo
, Seokin Hong
, Myung Kuk Yoon
, Yunho Oh
:
SAVector: Vectored Systolic Arrays. IEEE Access 12: 44446-44461 (2024) - 2023
- [j10]Awais Saeed
, Ubaid U. Fayyaz
, Ahsen Tahir
, Seokin Hong
, Tayyeb Mahmood
:
On the Positional Single Error Correction and Double Error Detection in Racetrack Memories. IEEE Access 11: 18300-18310 (2023) - [c21]Gwangeun Byeon, Seungtae Lee, Seongwook Kim, Yongjun Kim, Prashant J. Nair, Seokin Hong:
SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs. PACT 2023: 337-338 - [c20]Seungtae Lee, Jonghwan Ko, Seokin Hong:
Facto-CNN: Memory-Efficient CNN Training with Low-rank Tensor Factorization and Lossy Tensor Compression. ACML 2023: 662-677 - [c19]Seongwook Kim, Gwangeun Byeon, Sihyung Kim, Hyungjin Kim, Seokin Hong:
Conveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity. ICCD 2023: 423-431 - [c18]Gwangeun Byeon, Seongwook Kim, Seokin Hong:
Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers. ISOCC 2023: 207-208 - 2022
- [j9]Yongjun Kim
, Yuze Chen, Yongho Lee
, Limei Peng
, Seokin Hong
:
Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches. IEEE Access 10: 29419-29431 (2022) - [j8]Mingu Kang, Sangmin Hyun, Tae Hee Han
, Jungrae Kim
, Seokin Hong
:
On-the-Fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks. IEEE Access 10: 79730-79746 (2022) - [j7]Osang Kwon, Yongho Lee
, Seokin Hong
:
Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation. IEEE Access 10: 114552-114565 (2022) - [j6]Mukhammed Garifulla
, Juncheol Shin, Chanho Kim, Won Hwa Kim, Hye Jung Kim
, Jaeil Kim
, Seokin Hong
:
A Case Study of Quantizing Convolutional Neural Networks for Fast Disease Diagnosis on Portable Medical Devices. Sensors 22(1): 219 (2022) - [c17]Yongho Lee
, Osang Kwon, Seokin Hong:
Don't open row: rethinking row buffer policy for improving performance of non-volatile memories. DAC 2022: 823-828 - 2021
- [j5]Jinkwon Kim
, Seokin Hong
, Jeongkyu Hong
, Soontae Kim
:
CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems. IEEE Trans. Computers 70(7): 1132-1145 (2021) - [c16]Yuze Chen, Seokin Hong:
Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches. ICEIC 2021: 1-2 - 2020
- [c15]Beomjun Kim, Prashant J. Nair, Seokin Hong:
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches. ICCD 2020: 421-424
2010 – 2019
- 2019
- [j4]Wonyoung Lee
, Mincheol Kang
, Seokin Hong, Soontae Kim
:
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2033-2045 (2019) - [c14]Tian Jin, Seokin Hong:
Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization. ASPLOS 2019: 835-847 - [c13]Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. MICRO 2019: 453-465 - [i1]Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. CoRR abs/1909.00553 (2019) - 2018
- [c12]Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim
, Michael B. Healy:
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. MICRO 2018: 326-338 - 2017
- [c11]Yebin Lee, Hyeonggyu Kim, Seokin Hong, Soontae Kim
:
Partial Row Activation for Low-Power DRAM System. HPCA 2017: 217-228 - [c10]Michael B. Healy, Seokin Hong:
CramSim: controller and memory simulator. MEMSYS 2017: 83-85 - 2016
- [j3]Seokin Hong, Soontae Kim:
Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures. IEEE Trans. Computers 65(10): 2999-3012 (2016) - 2015
- [j2]Tayyeb Mahmood, Seokin Hong, Soontae Kim:
Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho. IEEE Trans. Computers 64(6): 1694-1706 (2015) - [j1]Seokin Hong, Soontae Kim:
A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU. IEEE Trans. Computers 64(9): 2433-2446 (2015) - 2014
- [c9]Seokin Hong, Jongmin Lee, Soontae Kim
:
Ternary cache: Three-valued MLC STT-RAM caches. ICCD 2014: 83-89 - 2013
- [c8]Seokin Hong, Soontae Kim
:
AVICA: an access-time variation insensitive L1 cache architecture. DATE 2013: 65-70 - [c7]Yebin Lee, Soontae Kim
, Seokin Hong, Jongmin Lee:
Skinflint DRAM system: Minimizing DRAM chip writes for low power. HPCA 2013: 25-34 - [c6]Tayyeb Mahmood, Soontae Kim
, Seokin Hong:
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling. HPCA 2013: 532-541 - 2011
- [c5]Jongmin Lee, Seokin Hong, Soontae Kim:
TLB index-based tagging for cache energy reduction. ISLPED 2011: 85-90 - [c4]Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong:
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. MICRO 2011: 420-429 - 2010
- [c3]Seokin Hong, Soontae Kim
:
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU. ICCD 2010: 342-349
2000 – 2009
- 2009
- [c2]Seokin Hong, Soontae Kim
:
TEPS: Transient Error Protection Utilizing Sub-word Parallelism. ISVLSI 2009: 286-291 - 2001
- [c1]Hyoshik Yu, YoungSu Lee, Seokin Hong, Jinwoo Kim, Hyunho Kim:
Rules of Convergence - What Would Become the Face of the Internet TV? PACIS 2001: 25
Coauthor Index
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last updated on 2024-05-26 00:47 CEST by the dblp team
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