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ORCIDIEEE Journal of Solid-State Circuits, Volume 47
Volume 47, Number 1, January 2012
- Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu:
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. 3-7 - Vivienne Sze, Anantha P. Chandrakasan:
A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding. 8-22 - Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS. 23-34 - Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28 nm 0.6 V Low Power DSP for Mobile Applications. 35-46 - Niklas Lotze, Yiannos Manoli:
A 62 mV 0.13 µ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic. 47-60 - Shyuan Liao, Yen-Shuo Chang, Chia-Hsin Wu, Hung-Chieh Tsai, Hsin-Hua Chen, Min Chen, Ching-Wen Hsueh, Jian-Bang Lin, Den-Kai Juang, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chih-Heng Shih, Barry Hong, Heng-Ruey Hsu, Chih-Yuan Wang, Meng-Shiang Lin, Wei-Hsiang Tseng, Che-Hsiung Yang, Lawrence Chen Lee, Ting-Jyun Jheng, Wen-Wei Yang, Ming-Yang Chao, Jyh-Shin Pan:
A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router. 61-74 - Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara:
A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology. 75-84 - Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi:
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. 85-96 - Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic:
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. 97-106 - Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun:
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. 107-116 - Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Mau-Chung Frank Chang
:
An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling. 117-130 - Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. 131-140 - Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan:
A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin. 141-150 - James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott:
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. 151-163 - Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh:
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. 164-176 - Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw:
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. 177-193 - Marcelo Yuffe, Moty Mehalel, Ernest Knoll, Joseph Shor, Tsvika Kurts, Eran Altshuler, Eyal Fayneh, Kosta Luria, Michael Zelikson:
A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor. 194-205 - Wonyoung Kim, David M. Brooks, Gu-Yeon Wei:
A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS. 206-219 - Denis Foley, Pankaj Bansal, Don Cherepacha, Robert Wasmuth, Aswin Gunasekar, Srinivasa Rao Gutta, Ajay Naini:
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices. 220-231 - Rikky Muller, Simone Gambini, Jan M. Rabaey:
A 0.013 mm2, 5 µW , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply. 232-243 - Emilia Noorsal, Kriangkrai Sooksood, Hongcheng Xu, Ralf Hornig, Joachim Becker, Maurits Ortmanns:
A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants. 244-256 - Albert Wang, Alyosha C. Molnar:
A Light-Field Image Sensor in 180 nm CMOS. 257-271 - Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito:
A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC. 272-283 - Kris Myny, Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil. 284-291 - Tarek Zaki, Frederik Ante, Ute Zschieschang, Joerg Butschke, Florian Letzkus, Harald Richter, Hagen Klauk, Joachim N. Burghartz:
A 3.3 V 6-Bit 100 kS/s Current-Steering Digital-to-Analog Converter Using Organic P-Type Thin-Film Transistors on Glass. 292-300 - Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier. 301-309 - Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo:
A 0.24-nJ/b Wireless Body-Area-Network Transceiver With Scalable Double-FSK Modulation. 310-322 - Seulki Lee, Long Yan, Taehwan Roh, Sunjoo Hong, Hoi-Jun Yoo:
A 75 µ W Real-Time Scalable Body Area Network Controller and a 25 µW ExG Sensor IC for Compact Sleep Monitoring Applications. 323-334 - Yu-Te Liao, Huanfen Yao, Andrew Lingley, Babak A. Parviz, Brian P. Otis:
A 3-µW CMOS Glucose Sensor for Wireless Contact-Lens Tear Glucose Monitoring. 335-344 - Alexander V. Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Solomon Assefa, Fuad E. Doany, Min Yang, Joris Van Campenhout, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov:
Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers. 345-354
Volume 47, Number 2, February 2012
- Sang-Young Kim, Gabriel M. Rebeiz:
A Low-Power BiCMOS 4-Element Phased Array Receiver for 76-84 GHz Radars and Communication Systems. 359-367 - Joohwa Kim, James F. Buckwalter:
A Switchless, Q-Band Bidirectional Transceiver in 0.12-µm SiGe BiCMOS Technology. 368-380 - Diptendu Ghosh, Ranjit Gharpurey:
A Power-Efficient Receiver Architecture Employing Bias-Current-Shared RF and Baseband With Merged Supply Voltage Domains and 1/f Noise Reduction. 381-391 - Donggu Im, Hongteuk Kim, Kwyro Lee:
A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts. 392-406 - Danilo Manstretta:
A Broadband Low-Power Low-Noise Active Balun With Second-Order Distortion Cancellation. 407-420 - Yuyu Chang, John C. Leete, Zhimin Zhou, Morteza Vadipour, Yin-Ting Chang, Hooman Darabi:
A Differential Digitally Controlled Crystal Oscillator With a 14-Bit Tuning Resolution and Sine Wave Outputs for Cellular Applications. 421-434 - Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno:
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. 435-443 - Wei-Te Lin, Tai-Haur Kuo:
A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection. 444-453 - Youngkil Choi, Wonho Tak, Younghyun Yoon, Jeongjin Roh, Sunwoo Kwon, Jinseok Koh:
A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup. 454-463 - Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
A 21 nV/√ Hz Chopper-Stabilized Multi-Path Current-Feedback Instrumentation Amplifier With 2 µ V Offset. 464-475 - Chenling Huang, Shantanu Chakrabartty:
An Asynchronous Analog Self-Powered CMOS Sensor-Data-Logger With a 13.56 MHz RF Programming Interface. 476-489 - Daniel Fernández, Luís Martínez-Alvarado, Jordi Madrenas:
A Translinear, Log-Domain FPAA on Standard CMOS Technology. 490-503 - Luis A. Camuñas-Mesa, Carlos Zamarreño-Ramos, Alejandro Linares-Barranco, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. 504-517 - Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim:
MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization. 518-535 - Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii:
An Embedded DRAM Technology for High-Performance NAND Flash Memories. 536-546 - Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim:
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. 547-559 - Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang:
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. 560-573 - Charalambos M. Andreou, Savvas Koudounas, Julius Georgiou:
A Novel Wide-Temperature-Range, 3.9 ppm/°C CMOS Bandgap Reference Circuit. 574-581
Volume 47, Number 3, March 2012
- Simone Gambini, John Crossley, Elad Alon, Jan M. Rabaey:
A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects. 586-598 - Jihwan Kim, Woonyun Kim, Hamhee Jeon, Yan-Yu Huang, Youngchang Yoon, Hyungwook Kim, Chang-Ho Lee, Kevin T. Kornegay:
A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer. 599-614 - Joohwa Kim, James F. Buckwalter:
A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS. 615-626 - Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. 627-640 - Matthew Loh, Azita Emami-Neyestanak:
A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O. 641-651 - Mehran M. Izad, Chun-Huat Heng:
A Pulse Shaping Technique for Spur Suppression in Injection-Locked Synthesizers. 652-664 - Jaewook Shin, Hyunchol Shin:
A 1.9-3.8 GHz ΔΣ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency. 665-675 - Brandon Rumberg, David W. Graham:
A Low-Power Magnitude Detector for Analysis of Transient-Rich Signals. 676-685 - Federico Guanziroli, Rossella Bassoli, Carlo Crippa, Daniele Devecchi, Germano Nicollini:
A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction. 686-698 - Matteo Crotti, Ivan Rech, Massimo Ghioni:
Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting. 699-708 - Fridolin Michel, Michiel Steyaert:
A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS. 709-721 - Zhenglin Yang, Libin Yao, Yong Lian:
A 0.5-V 35-µW 85-dB DR Double-Sampled ΔΣ Modulator for Audio Applications. 722-735 - Young Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim:
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS. 736-743 - Fred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic:
Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors. 744-756 - Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic:
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example. 757-768 - Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang:
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. 769-780
Volume 47, Number 4, April 2012
- Makoto Nagata, Vivek De:
Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. 795-796 - Yu-Chi Su, Keng-Yen Huang, Tse-Wei Chen, Yi-Min Tsai, Shao-Yi Chien, Liang-Gee Chen:
A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications. 797-809 - Shinichiro Uemura, Yukio Hiraoka, Takayuki Kai, Shiro Dosho:
Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. 810-816 - Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. 817-831 - Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno:
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. 832-840 - Mohammad K. Al-Ghamdi, Anas A. Hamoui:
A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a ΔΣ-Modulator Controller With a Scalable Sampling Frequency. 841-851 - Tzu-Chi Huang, Chun-Yu Hsieh, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Ming-Wei Lee:
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control. 852-862 - John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman:
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. 863-874 - Dong-Woo Jee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC. 875-883 - Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman:
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. 884-896 - Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf:
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. 897-910 - Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. 911-925 - Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. 926-937 - E-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang:
Power Optimized ADC-Based Serial Link Receiver. 938-951 - Chintan Thakkar, Lingkai Kong, Kwangmo Jung, Antoine Frappé, Elad Alon:
A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS. 952-968 - Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi:
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. 969-980 - Chulbum Kim, Jinho Ryu, Tae-Sung Lee, Hyunggon Kim, Jaewoo Lim, Jaeyong Jeong, Seonghwan Seo, Hongsoo Jeon, Bokeun Kim, Inyoul Lee, Dooseop Lee, Pansuk Kwak, Seongsoon Cho, Yongsik Yim, Changhyun Cho, Woopyo Jeong, Kwang-Il Park, Jin-Man Han, Duheon Song, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun:
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. 981-989 - Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. 990-1002 - Frank Van de Sande, Nico Lugil, Filip Demarsin, Zeger Hendrix, Alvin Andries, Peter Brandt, William Anklam, Jeffery S. Patterson, Brian Miller, Michael Rytting, Mike Whaley, Bob Jewett, Jacky Liu, Jake Wegman, Ken Poulton:
A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz fT BiCMOS Process. 1003-1012 - Chun-Ying Chen, Jiangfeng Wu, Juo-Jung Hung, Tianwei Li, Wenbo Liu, Wei-Ta Shih:
A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm2 and 500 mW in 40 nm Digital CMOS. 1013-1021 - Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. 1022-1030 - Gordon Wan, Xiangli Li, Gennadiy Agranov, Marc Levoy, Mark Horowitz:
CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography. 1031-1042 - Hua Gao, Ross M. Walker, Paul Nuyujukian, Kofi A. A. Makinwa, Krishna V. Shenoy, Boris Murmann, Teresa H. Meng:
HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 µm CMOS. 1043-1055 - Paul Peng Liu, Karl Skucha, Yida Duan, Mischa Megens, Jungkyu Kim, Igor I. Izyumin, Simone Gambini, Bernhard E. Boser:
Magnetic Relaxation Detector for Microbead Labels. 1056-1064
Volume 47, Number 5, May 2012
- Un-Ku Moon:
New Associate Editors. 1071-1072 - Georg Böck:
Overview for the Special Section on the 2011 Radio Frequency Integrated Circuits (RFIC) Symposium. 1073-1074 - Laurent Negre, David Roy, Florian Cacho, Patrick Scheer, Sebastien Jan, Samuel Boret, Daniel Gloria, Gérard Ghibaudo:
Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses. 1075-1083 - Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi:
A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems. 1084-1093 - François Belmas, Frédéric Hameau, Jean-Michel Fournier:
A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS. 1094-1103 - Toshifumi Nakatani, Jeremy Rode, Donald F. Kimball, Lawrence E. Larson, Peter M. Asbeck:
Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications. 1104-1112 - Debopriyo Chowdhury, Siva V. Thyagarajan, Lu Ye, Elad Alon, Ali M. Niknejad:
A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters. 1113-1122 - Ward S. Titus, John G. Kenney:
A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs. 1123-1130 - Jianhua Lu, Ning-Yi Wang, Mau-Chung Frank Chang:
A Compact and Low Power 5-10 GHz Quadrature Local Oscillator for Cognitive Radio Applications. 1131-1140 - Subhanshu Gupta, Daibashish Gangopadhyay, Hasnain Lakdawala, Jacques Christophe Rudell, David J. Allstot:
A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS. 1141-1153 - Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang, Li-Rong Zheng:
The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator. 1154-1164 - Heesong Seo, In Young Choi, Changjoon Park, Jehyung Yoon, Bumman Kim:
A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX. 1165-1174 - Marc Tiebout, Hans-Dieter Wohlmuth, Herbert Knapp, Raffaele Salerno, Michael Druml, Mirjana Rest, Johann Kaeferboeck, Johann Wuertele, Sherif Sayed Ahmed, Andreas Schiessl, Ralf Juenemann, Anna Zielska:
Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology. 1175-1184 - Muhammad Hassan, Lawrence E. Larson, Vincent W. Leung, Peter M. Asbeck:
A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications. 1185-1198 - Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile. 1199-1208 - Jing Guo, George Jie Yuan, Jiageng Huang, Jessica Ka-Yan Law, Chi-Kong Yeung, Mansun Chan:
32.9 nV/rt Hz - 60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC. 1209-1220 - Xicheng Jiang, Jungwoo Song, Jianlong Chen, Vinay Chandrasekhar, Sherif Galal, Felix Y. L. Cheung, Darwin Cheung, Todd Brooks:
A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 µm CMOS. 1221-1231 - Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda:
A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. 1232-1241 - Yingchieh Ho, Chauchin Su:
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters. 1242-1251 - Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. 1252-1260
Volume 47, Number 6, 2012
- Takahiro Nakamura, Toru Masuda, Katsuyoshi Washio, Hiroshi Kondoh:
A Push-Push VCO With 13.9-GHz Wide Tuning Range Using Loop-Ground Transmission Line for Full-Band 60-GHz Transceiver. 1267-1277 - Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio:
Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators. 1278-1294 - Guansheng Li, Li Liu, Yiwu Tang, Ehsan Afshari:
A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching. 1295-1308 - James F. Buckwalter, Xuezhe Zheng, Guoliang Li, Kannan Raj, Ashok V. Krishnamoorthy:
A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process. 1309-1322 - Chang Liu, Yue-Peng Yan, Wang Ling Goh, Yong-Zhong Xiong, Li-Jun Zhang, Mohammad Madihian:
A 5-Gb/s Automatic Gain Control Amplifier With Temperature Compensation. 1323-1333 - Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, Hsin-Shu Chen:
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. 1334-1343 - Jia-Ming Liu, Shih-Hsiung Chien, Tai-Haur Kuo:
A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design. 1344-1354 - Rosario Pagano, Michael Baker, Russell E. Radke:
A 0.18-μm Monolithic Li-Ion Battery Charger for Wireless Devices Based on Partial Current Sensing and Adaptive Reference Voltage. 1355-1368 - Dominic Maurath, Philipp F. Becker, Dirk Spreemann, Yiannos Manoli:
Efficient Energy Harvesting With Electromagnetic Energy Transducers Using Active Low-Voltage Rectification and Maximum Power Point Tracking. 1369-1380 - Hossein Miri Lavasani, Wanling Pan, Brandon Harrington, Reza Abdolvand, Farrokh Ayazi:
Electronic Temperature Compensation of Lateral Bulk Acoustic Resonator Reference Oscillators Using Enhanced Series Tuning Technique. 1381-1393 - Marek Gersbach, Yuki Maruyama, Rahmadi Trimananda, Matthew W. Fishburn, David Stoppa, Justin A. Richardson, Richard Walker, Robert K. Henderson, Edoardo Charbon:
A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology. 1394-1407 - Ruoyu Xu, Bing Liu, George Jie Yuan:
A 1500 fps Highly Sensitive 256 , ˟, 256 CMOS Imaging Sensor With In-Pixel Calibration. 1408-1418 - Song-Nien Tang, Chi-Hsiang Liao, Tsin-Yuan Chang:
An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems. 1419-1435 - Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. 1436-1447 - Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide:
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. 1448-1459 - Teruyoshi Hatanaka, Ken Takeuchi:
NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD. 1460-1468 - Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang:
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. 1469-1482 - Pi-Feng Chiu, Meng-Fan Chang, Che-Wei Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu, Yu-Sheng Chen, Ming-Jinn Tsai:
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. 1483-1496 - Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668]. 1497
Volume 47, Number 7, July 2012
- Atila Alvandpour, Patrick Reynaert, Trond Ytterdal:
Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC). 1511-1514 - Vadim Ivanov, Ralf Brederlow, Johannes Gerber:
An Ultra Low Power Bandgap Operational at Supply From 0.75 V. 1515-1523 - Lûtsen Dooper, Marco Berkhout:
A 3.4 W Digital-In Class-D Audio Amplifier in 0.14µm CMOS. 1524-1534 - Mahdi Kashmiri, Kamran Souri, Kofi A. A. Makinwa:
A Scaled Thermal-Diffusivity-Based 16 MHz Frequency Reference in 0.16 µm CMOS. 1535-1545 - Sebastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschirotto, Angelo Nagari:
A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop. 1546-1556 - Robert C. N. Pilawa-Podgurski, David J. Perreault:
Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS. 1557-1567 - Wen-Shen Chou, Tzu-Chi Huang, Yu-Huei Lee, Yao-Yi Yang, Yi-Ping Su, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Kuei-Ann Wen, Ying-Chih Hsu, Yung-Chow Peng, Fu-Lung Hsueh:
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter. 1568-1584 - Dai Zhang, Ameya Bhide, Atila Alvandpour:
A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-µm CMOS for Medical Implant Devices. 1585-1593 - Pieter Harpe, Ben Busze, Kathleen Philips, Harmke de Groot:
A 0.47-1.6 mW 5-bit 0.5-1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios. 1594-1602 - Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC. 1603-1614 - Ankesh Jain, Muthusubramaniam Venkatesan, Shanthi Pavan:
Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique. 1615-1625 - Ping Lu, Antonio Liscidini, Pietro Andreani:
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. 1626-1635 - Mikko Kaltiokallio, Ville Saari, Sami Kallioinen, Aarno Pärssinen, Jussi Ryynänen:
Wideband 2 to 6 GHz RF Front-End With Blocker Filtering. 1636-1645 - Wei Tai, Hongtao Xu, Ashoke Ravi, Hasnain Lakdawala, Ofir B. Degani, L. Richard Carley, Yorgos Palaskas:
A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement. 1646-1658 - Ercan Kaymaksut, Patrick Reynaert:
Transformer-Based Uneven Doherty Power Amplifier in 90 nm CMOS for WLAN Applications. 1659-1671 - Jos Bergervoet, Domine Leenaerts, Gerben W. de Jong, Edwin van der Heijden, Jan-Willem Lobeek, Alexander Simin:
A 1.95 GHz Sub-1 dB NF, +40 dBm OIP3 WCDMA LNA Module. 1672-1680 - Pieter A. J. Nuyts, Peter Singerl, Franz Dielacher, Patrick Reynaert, Wim Dehaene:
A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS. 1681-1692 - Michael Georgas, Jason Orcutt, Rajeev J. Ram, Vladimir Stojanovic:
A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI. 1693-1702 - Zhichao Tan, Saleh Heidary Shalmany, Gerard C. M. Meijer, Michiel A. P. Pertijs:
An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation. 1703-1711 - Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans:
Analog Building Blocks for Organic Smart Sensor Systems in Organic Thin-Film Transistor Technology on Flexible Plastic Foil. 1712-1720 - Mikail Yücetas, Mika Pulkkinen, Antti Kalanti, Jarno Salomaa, Lasse Aaltonen, Kari Halonen:
A High-Resolution Accelerometer With Electrostatic Damping and Improved Supply Sensitivity. 1721-1730 - Jian Guo, Sameer R. Sonkusale:
A 65 nm CMOS Digital Phase Imager for Time-Resolved Fluorescence Imaging. 1731-1742 - Jonathan Müller, Bruno Stefanelli, Antoine Frappé, Lu Ye, Andreia Cathelin, Ali M. Niknejad, Andreas Kaiser:
A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters. 1743-1756 - Pieter De Wit, Georges G. E. Gielen:
Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS. 1757-1767 - Arnoud P. van der Wel, Gerrit den Besten:
A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS. 1768-1775 - Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. 1776-1783 - Bram Rooseleer, Stefan Cosemans, Wim Dehaene:
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link. 1784-1796
Volume 47, Number 8, August 2012
- Hasnain Lakdawala, Alvin Leng Sun Loke:
Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference. 1798-1799 - Ralph D. Mason, Justin Fortier, Christopher A. DeVries:
Complete SOC Transceiver in 0.18 µm CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking. 1800-1809 - Yanjie Wang, Hua Wang, Chris Hull, Shmuel Ravid:
A Transformer-Based Broadband Front-End Combo in Standard CMOS. 1810-1819 - Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka:
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion. 1820-1827 - Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli:
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. 1828-1841 - Kangmin Hu, Rui Bai, Tao Jiang, Chao Ma, Ahmed Ragab, Samuel Palermo, Patrick Yin Chiang:
0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking. 1842-1853 - I-Ning Ku, Zhiwei Xu, Yen-Cheng Kuan, Yen-Hsiang Wang, Mau-Chung Frank Chang:
A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications. 1854-1865 - Kentaro Yamamoto, Anthony Chan Carusone:
A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs. 1866-1883 - Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania:
A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. 1884-1895 - Wu-Hsin Chen, Wing-Fai Loke, Byunghoo Jung:
A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices. 1896-1907 - Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello:
A Dither-Less All Digital PLL for Cellular Transmitters. 1908-1920 - Sherif Galal, Hui Zheng, Khaled Abdelfattah, Vinay Chandrasekhar, Iuri Mehr, Alex Jianzhong Chen, John Platenak, Nir Matalon, Todd Brooks:
A 60 mW Class-G Stereo Headphone Driver for Portable Battery-Powered Devices. 1921-1934 - Noah Sturcken, Michele Petracca, Steve B. Warren, Paolo Mantovani, Luca P. Carloni, Angel V. Peterchev, Kenneth L. Shepard:
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI. 1935-1945 - Justin Shi, Eric G. Soenen, Alan Roth, Ying-Chih Hsu, Martin Kinyua:
Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS. 1946-1959
Volume 47, Number 9, September 2012
- Un-Ku Moon:
New Associate Editor. 1963 - Fa Foster Dai:
Introduction to the Special Section on the 25th Bipolar/BiCMOS Circuits and Technology Meeting. 1964-1965 - Benjamin Laemmle, Gabor Vinci, Linus Maurer, Robert Weigel, Alexander Koelpin:
A 77-GHz SiGe Integrated Six-Port Receiver Front-End for Angle-of-Arrival Detection. 1966-1973 - Nils Pohl, Tobias Klein, Klaus Aufinger, Hans-Martin Rein:
A Low-Power Wideband Transmitter Front-End Chip for 80 GHz FMCW Radar Systems With Integrated 23 GHz Downconverter VCO. 1974-1980 - Yi Zhao, John R. Long:
A Wideband, Dual-Path, Millimeter-Wave Power Amplifier With 20 dBm Output Power and PAE Above 15% in 130 nm SiGe-BiCMOS. 1981-1997 - Prabir K. Saha, Duane C. Howard, Subramaniam Shankar, Ryan Diestelhorst, Troy D. England, John D. Cressler:
A 6-20 GHz Adaptive SiGe Image Reject Mixer for a Self-Healing Receiver. 1998-2006 - Yan Li, Jerry Lopez, Cliff Schecht, Ruili Wu, Donald Y. C. Lie:
Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications. 2007-2018 - Hamhee Jeon, Yunseo Park, Yan-Yu Huang, Jihwan Kim, Kun-Seok Lee, Chang-Ho Lee, J. Stevenson Kenney:
A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler. 2019-2032 - Erik Pankratz, Edgar Sánchez-Sinencio:
Multiloop High-Power-Supply-Rejection Quadrature Ring Oscillator. 2033-2048 - Frankie Liu, Dinesh Patil, Jon K. Lexau, Philip Amberg, Michael Dayringer, Jonathan Gainsley, Hesam Fathi Moghadam, Xuezhe Zheng, John E. Cunningham, Ashok V. Krishnamoorthy, Elad Alon, Ron Ho:
10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS. 2049-2067 - Hae-Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park:
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. 2068-2079 - Yunzhi Dong, Kenneth W. Martin:
A High-Speed Fully-Integrated POF Receiver With Large-Area Photo Detectors in 65 nm CMOS. 2080-2092 - Ying Cao, Wouter De Cock, Michiel Steyaert, Paul Leroux:
1-1-1 MASH Δ Σ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping. 2093-2106 - Aldo Pena-Perez, Edoardo Bonizzoni, Franco Maloberti:
A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order Σ Δ Modulator. 2107-2118 - Shankar Guhados, Paul J. Hurst, Stephen H. Lewis:
A Pipelined ADC With Metastability Error Rate <10-15 Errors/Sample. 2119-2128 - Ruoyu Xu, Bing Liu, George Jie Yuan:
Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering. 2129-2140 - Justin Kyung-Ryun Kim, Boris Murmann:
A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration. 2141-2151 - Rong Wu, Youngcheol Chae, Johan H. Huijsing, Kofi A. A. Makinwa:
A 20-b ± 40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers. 2152-2163 - Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis:
Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation. 2164-2173 - Craig Schlottmann, Samuel A. Shapero, Stephen Nease, Paul E. Hasler:
A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing. 2174-2184 - Thorsten Hehn, Friedrich Hagedorn, Dominic Maurath, Djordje Marinkovic, Ingo Kuehne, Alexander Frey, Yiannos Manoli:
A Fully Autonomous Integrated Interface Circuit for Piezoelectric Harvesters. 2185-2198 - Saurav Bandyopadhyay, Anantha P. Chandrakasan:
Platform Architecture for Solar, Thermal, and Vibration Energy Combining With MPPT and Single Inductor. 2199-2215 - Yikai Wang, Dongsheng Ma:
A 450-mV Single-Fuel-Cell Power Management Unit With Switch-Mode Quasi-V2 Hysteretic Control and Automatic Startup on 0.35-µm Standard CMOS Process. 2216-2226 - Sau Siong Chong, Pak Kwong Chan:
Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load. 2227-2234 - Tsung-Han Yu, Chia-Hsiang Yang, Danijela Cabric, Dejan Markovic:
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios. 2235-2245 - Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. 2246-2257 - Hiroki Inoue, Takanori Matsuzaki, Shuhei Nagatsuka, Yutaka Okazaki, Toshinari Sasaki, Kousei Noda, Daisuke Matsubayashi, Takahiko Ishizu, Tatsuya Onuki, Atsuo Isobe, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Jun Koyama, Shunpei Yamazaki:
Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor. 2258-2265
Volume 47, Number 10, October 2012
- Un-Ku Moon:
New Associate Editor. 2279 - Payam Heydari:
Introduction to the 33rd Annual IEEE Compound Semiconductor Integrated Circuit Symposium. 2280-2281 - Simon J. Mahon, Alan C. Young, Anthony E. Parker:
Common-Gate Load-Pull With Q-Band Application. 2282-2290 - Vesna Radisic, Kevin M. K. H. Leong, Stephen Sarkozy, Xiaobing (Gerry) Mei, Wayne Yoshida, Po-Hsin Liu, William R. Deal, Richard Lai:
220-GHz Solid-State Power Amplifier Modules. 2291-2297 - Jonmei J. Yan, Chin Hsia, Donald F. Kimball, Peter M. Asbeck:
Design of a 4-W Envelope Tracking Power Amplifier With More Than One Octave Carrier Bandwidth. 2298-2308 - Ha Trong Than, George W. Sun, Geovanni S. Cuellar, Jiyang Zeng, Nate T. Schultz, Michael E. Moya, Younkyu Chung, Blythe C. Deckman, Michael P. DeLisio:
Design and Performance of a 600-WC-Band Amplifier Using Spatially Combined GaAs FETs for Satellite Communications. 2309-2315 - Kevin W. Kobayashi:
An 8-W 250-MHz to 3-GHz Decade-Bandwidth Low-Noise GaN MMIC Feedback Amplifier With > +51-dBm OIP3. 2316-2326 - Parrish Ralston, Marcus Oliver, Krishna Vummidi, Sanjay Raman:
Liquid-Metal Vertical Interconnects for Flip Chip Assembly of GaAs C-Band Power Amplifiers Onto Micro-Rectangular Coaxial Transmission Lines. 2327-2334 - Chikuang Yu, Chieh-Lin Wu, Sandeep Kshattry, Yang-Hun Yun, Choong-Yul Cha, Hisashi Shichijo, Kenneth K. O:
Compact, High Impedance and Wide Bandwidth Detectors for Characterization of Millimeter Wave Performance. 2335-2343 - Jung-Dong Park, Shinwon Kang, Ali M. Niknejad:
A 0.38 THz Fully Integrated Transceiver Utilizing a Quadrature Push-Push Harmonic Circuitry in SiGe BiCMOS. 2344-2354 - Zhiming Chen, Chun-Cheng Wang, Hsin-Cheng Yao, Payam Heydari:
A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna. 2355-2371 - Philip A. Godoy, SungWon Chung, Taylor W. Barton, David J. Perreault, Joel L. Dawson:
A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS. 2372-2384 - Hajir Hedayati, Mohamed Mobarak, Guillaume Varin, Philippe Meunier, Patrice Gamand, Edgar Sánchez-Sinencio, Kamran Entesari:
A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network. 2385-2404 - Dae-Young Yoon, Chang-Jin Jeong, Justin Cartwright, Ho-Yong Kang, Seok-Kyun Han, Nae-Soo Kim, Dong Sam Ha, Sang-Gug Lee:
A New Approach to Low-Power and Low-Latency Wake-Up Receiver System for Wireless Sensor Nodes. 2405-2419 - Meisam Honarvar Nazari, Azita Emami-Neyestanak:
A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation. 2420-2432 - Pyoungwon Park, Dongmin Park, SeongHwan Cho:
A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL. 2433-2443 - Tao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Kangmin Hu, Patrick Yin Chiang:
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS. 2444-2453 - Chih-Wen Lu, Ping-Yeh Yin, Ching-Min Hsiao, Mau-Chung Frank Chang, Yo-Sheng Lin:
A 10-bit Resistor-Floating-Resistor-String DAC (RFR-DAC) for High Color-Depth LCD Driver ICs. 2454-2466 - Ahmed A. Helmy, Hyung-Joon Jeon, Yung-Chung Lo, Andreas J. Larsson, Raghavendra Kulkarni, Jusung Kim, José Silva-Martínez, Kamran Entesari:
A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer. 2467-2483 - Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda:
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. 2484-2495 - Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. 2496-2504 - Dong Jiao, Bongjin Kim, Chris H. Kim:
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation. 2505-2516 - Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. 2517-2526 - Junghyup Lee, SeongHwan Cho:
A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS. 2527-2533 - Mingoo Seok, Gyouho Kim, David T. Blaauw, Dennis Sylvester:
A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V. 2534-2545
Volume 47, Number 11, November 2012
- Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee:
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). 2551-2553 - Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. 2554-2562 - Yu-Huei Lee, Chao-Chang Chiu, Shen-Yu Peng, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Chen-Chih Huang, Tsung-Yen Tsai:
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System. 2563-2575 - Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro:
1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. 2576-2585 - Kuo-Hsin Chen, Yen-Shun Hsu:
A High-PSRR Reconfigurable Class-AB/D Audio Amplifier Driving a Hands-Free/Receiver 2-in-1 Loudspeaker. 2586-2603 - Jon Guerber, Hariprasath Venkatram, Manideep Gande, Allen Waters, Un-Ku Moon:
A 10-b Ternary SAR ADC With Quantization Time Information Utilization. 2604-2613 - Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. 2614-2626 - Alvin Leng Sun Loke, Bruce Andrew Doyle, Sanjeev K. Maheshwari, Dennis Michael Fischette, Charles Lin Wang, Tin Tin Wee, Emerson S. Fang:
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. 2627-2642 - Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. 2643-2653 - Sanming Hu, Yong-Zhong Xiong, Bo Zhang, Lei Wang, Teck-Guan Lim, Minkyu Je, Mohammad Madihian:
A SiGe BiCMOS Transmitter/Receiver Chipset With On-Chip SIW Antennas for Terahertz Applications. 2654-2664 - Sam Chun-Geik Tan, Fei Song, Renliang Zheng, Jiqing Cui, Guoqin Yao, Litian Tang, Yuejin Yang, Dandan Guo, Alexander Tanzil, Junmin Cao, Ming Kong, KianTiong Wong, Soong Lin Chew, Chee-Lee Heng, Osama Shana'a, Guang-Kaai Dehng:
An Ultra-Low-Cost High-Performance Bluetooth SoC in 0.11-µm CMOS. 2665-2677 - Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo:
A Low-Energy Crystal-Less Double-FSK Sensor Node Transceiver for Wireless Body-Area Network. 2678-2692 - I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology. 2693-2700 - Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi:
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. 2701-2710 - Junyoung Park, Joonsoo Kwon, Jinwook Oh, Seungjin Lee, Joo-Young Kim, Hoi-Jun Yoo:
A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine. 2711-2723 - Rahul Rithe, Chih-Chi Cheng, Anantha P. Chandrakasan:
Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding. 2724-2736 - Andrea Barbieri, Germano Nicollini:
100+dB A-Weighted SNR Microphone Preamplifier With On-Chip Decoupling Capacitors. 2737-2750 - Phanumas Khumsat, Apisak Worapishet:
A 0.5-V R-MOSFET-C Filter Design Using Subthreshold R-MOSFET Resistors and OTAs With Cross-Forward Common-Mode Cancellation Technique. 2751-2762 - He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. 2763-2772 - Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho:
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. 2773-2782 - Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. 2783-2795 - Jens Masuch, Manuel Delgado-Restituto:
A 190-µW zero-IF GFSK Demodulator With a 4-b Phase-Domain ADC. 2796-2806 - Sanu Mathew, Suresh Srinivasan, Mark A. Anders, Himanshu Kaul, Steven Hsu, Farhana Sheikh, Amit Agarwal, Sudhir Satpathy, Ram Krishnamurthy:
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. 2807-2821 - Ritu Raj Singh, Lian Leng, Axel Guenther, Roman Genov:
A CMOS-Microfluidic Chemiluminescence Contact Imaging Microsystem. 2822-2833 - Seong-Jin Kim, James D. K. Kim, Byongmin Kang, KeeChang Lee:
A CMOS Image Sensor Based on Unified Pixel Architecture With Time-Division Multiplexing Scheme for Color and Depth Image Acquisition. 2834-2845 - Ming Gu, Shantanu Chakrabartty:
Subthreshold, Varactor-Driven CMOS Floating-Gate Current Memory Array With Less Than 150-ppm/°K Temperature Sensitivity. 2846-2856
Volume 47, Number 12, 2012
- Pradeep Shettigar, Shanthi Pavan:
Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs. 2865-2879 - Bob Verbruggen, Masao Iriguchi, Jan Craninckx:
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. 2880-2887 - Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai:
A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW. 2888-2897 - Jeffrey Fredenburg, Michael P. Flynn:
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC. 2898-2904 - Yun Chai, Jieh-Tsorng Wu:
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC. 2905-2915 - Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. 2916-2927 - Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Ring Amplifiers for Switched Capacitor Circuits. 2928-2942 - David Murphy, Hooman Darabi, Asad A. Abidi, Amr Amin Hafez, Ahmad Mirzaei, Mohyee Mikhemar, Mau-Chung Frank Chang:
A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications. 2943-2963 - Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier. 2964-2973 - Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. 2974-2988 - Dongmin Park, SeongHwan Cho:
A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS. 2989-2998 - Richard Al Hadi, Hani Sherry, Janus Grzyb, Yan Zhao, Wolfgang Forster, H. M. Keller, Andreia Cathelin, Andreas Kaiser, Ullrich R. Pfeiffer:
A 1 k-Pixel Video Camera for 0.7-1.1 Terahertz Imaging Applications in 65-nm CMOS. 2999-3012 - Kaushik Sengupta, Ali Hajimiri:
A 0.28 THz Power-Generation and Beam-Steering Array in CMOS Based on Distributed Active Radiators. 3013-3031 - Yahya M. Tousi, Omeed Momeni, Ehsan Afshari:
A Novel CMOS High-Power Terahertz VCO Based on Coupled Oscillators: Theory and Implementation. 3032-3042 - Jason T. Stauth, Michael D. Seeman, Kapil Kesarwani:
A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management. 3043-3054 - Jong-Pil Im, Se-Won Wang, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting. 3055-3067 - Angelo Nagari, Emmanuel Allier, Francois Amiard, Vincent Binet, Christian Fraisse:
An 8 Ω 2.5 W 1%-THD 104 dB(A)-Dynamic-Range Class-D Audio Amplifier With Ultra-Low EMI System and Current Sensing for Speaker Protection. 3068-3080 - Jong Tae Hwang, Moon Sang Jung, Dae Ho Kim, Jun Hong Lee, Minho Jung, Jong-Shin Ha:
Off-the-Line Primary Side Regulation LED Lamp Driver With Single-Stage PFC and TRIAC Dimming Using LED Forward Voltage and Duty Variation Tracking Control. 3081-3094 - Karl Norling, Christian Lindholm, Dieter Draxelmayr:
An Optimized Driver for SiC JFET-Based Switches Enabling Converter Operation With More Than 99% Efficiency. 3095-3104 - Milad Darvishi, Ronan A. R. van der Zee, Eric A. M. Klumperink, Bram Nauta:
Widely Tunable 4th Order Switched Gm-C Band-Pass Filter Based on N-Path Filters. 3105-3119 - Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
Analog Filter Design Using Ring Oscillator Integrators. 3120-3129 - Shadi Youssef, Ronan A. R. van der Zee, Bram Nauta:
Active Feedback Technique for RF Channel Selection in Front-End Receivers. 3130-3144 - Lei Wang, Yong Lian, Chun-Huat Heng:
3-5 GHz 4-Channel UWB Beamforming Transmitter With 1° Scanning Resolution Through Calibrated Vernier Delay Line in 0.13-µm CMOS. 3145-3159 - Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa:
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication. 3160-3171 - Dixian Zhao, Shailesh Kulkarni, Patrick Reynaert:
A 60-GHz Outphasing Transmitter in 40-nm CMOS. 3172-3183 - Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas:
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. 3184-3196 - Xiongchuan Huang, Ao Ba, Pieter Harpe, Guido Dolmans, Harmke de Groot, Jeffrey Richard Long:
A 915 MHz, Ultra-Low Power 2-Tone Transceiver With Enhanced Interference Resilience. 3197-3207 - Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan:
A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link. 3208-3219 - Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman:
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. 3220-3231 - John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman:
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. 3232-3248 - Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Wei Zhang, Tamer A. Ali, Nick Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. 3249-3260 - Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng:
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. 3261-3272
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