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ORCID3DIC 2014: Kinsdale, Ireland
- 2014 International 3D Systems Integration Conference, 3DIC 2014, Kinsdale, Ireland, December 1-3, 2014. IEEE 2014, ISBN 978-1-4799-8472-5
- Dorota S. Temple, Dean Malta, Erik P. Vick, Matthew R. Lueck, Scott H. Goodwin, Mark S. Muzilla, Christopher M. Masterjohn, Mark R. Skokan:
Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test. 1-7 - Paul D. Franzon
, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel:
3D-enabled customizable embedded computer (3DECC). 1-3 - Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto:
Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. 1-5 - Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi:
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. 1-4 - Joeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne:
Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. 1-7 - Fumihiro Inoue, Harold Philipsen, Marleen H. van der Veen, Kevin Vandersmissen, Stefaan Van Huylenbroeck, Herbert Struyf, Tetsu Tanaka:
Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias. 1-4 - Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
A built-in supply current test circuit for electrical interconnect tests of 3D ICs. 1-6 - Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 1-7 - Robert Fischbach, Andy Heinig, Peter Schneider:
Design rule check and layout versus schematic for 3D integration and advanced packaging. 1-7 - Jonghoon J. Kim, Bumhee Bae, Sukjin Kim, Sunkyu Kong, Heegon Kim, Daniel H. Jung, Joungho Kim:
Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICs. 1-6 - Khadim Dieng, Philippe Artillan, Cédric Bermond, Olivier Guiller, Thierry Lacrevaz, Sylvain Joblot, Gregory Houzet, Alexis Farcy, Yann Lamy, Bernard Fléchet:
Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer. 1-8 - K. W. Lee, Chisato Nagai, Ai Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tanaka Tanaka, Mitsumasa Koyanagi:
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. 1-4 - Jing Tao, Alan Mathewson, Kafil M. Razeeb:
Bumpless interconnects formed with nanowire ACF for 3D applications. 1-6 - Oded Raz, Pinxiang Duan, Harm J. S. Dorren:
Simple and low cost technique for stacking known good dies to create compact 3D stacked parallel optics assemblies. 1-4 - X. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne:
Analysis of 3D interconnect performance: Effect of the Si substrate resistivity. 1-4 - Katsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama:
Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. 1-6 - Mariappan Murugesan, Takafumi Fukushima, Ji Chel Bea, K. W. Lee, Mitsu Koyanagi, Y. Imai, S. Kimura, Tetsu Tanaka:
Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI. 1-4 - Emma Kowalczuk, Arnab Bhattacharya, Ka Chung Lee, Jesse Alton, Martin Igarashi, Stephane Barbeau:
Fault localisation of defects using Electro Optical Terahertz Pulse Reflectometry and 3D EM modelling with Virtual Known Good Device. 1-4 - Mehdi Saedi, Kambiz Samadi, Arpit Mittal, Rajat Mittal:
Thermal implications of mobile 3D-ICs. 1-7 - Yoriko Mizushima, Young-Suk Kim, Tomoji Nakamura, Shoichi Kodama, Nobuhide Maeda, Koji Fujimoto, Takayuki Ohba:
Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure. 1-5 - Bui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi:
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 1-4 - Cristiano Santos, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Augusto da Luz Reis:
Thermal performance of 3D ICs: Analysis and alternatives. 1-7 - Keiji Matsumoto, Hiroyuki Mori, Yasumitsu Orii:
Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack. 1-6 - Severin Zimmermann, Thomas Brunschwiler, Brian R. Burg, Jonas Zuercher, Guo Hong, Dimos Poulikakos, Mario Baum, Christian Hofmann:
Characterization of particle beds in percolating thermal underfills based on centrifugation. 1-7 - Chaoqi Zhang, Paragkumar Thadesar, Muneeb Zia, Thomas E. Sarvey, Muhannad S. Bakir:
Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects. 1-4 - Cristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain, Jean-Philippe Colonna, Pascal Vivet, Andras Borbely, Ricardo Reis, M. Haykel Ben Jamaa, Vincent Fiori, Alexis Farcy:
Using TSVs for thermal mitigation in 3D circuits: Wish and truth. 1-8 - Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi:
Analysis of thermal stress distribution for TSV with novel structure. 1-4 - Young Sik Song, Yunho Han, Tai Hong Yim:
Conventional magnetron sputtering of metal seed layers on high aspect ratio vias with tilting. 1-4 - Daniel H. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi:
Fault detection and isolation of multiple defects in through silicon via (TSV) channel. 1-5 - Armin Grünewald, Michael G. Wahl, Rainer Brück:
Manufacturing and test assistance for 3D-Integrated heterogeneous systems. 1-6 - Randy Widialaksono, Wenxu Zhao, W. Rhett Davis, Paul D. Franzon:
Leveraging 3D-IC for on-chip timing uncertainty measurements. 1-4 - Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
On-chip checkpointing with 3D-stacked memories. 1-6 - Yang Zhang, Thomas E. Sarvey, Muhannad S. Bakir:
Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation. 1-5 - James F. Rohan, Declan Casey, Monika Zygowska, Michael Moore, Brian Shanahan:
Electroless metal deposition for IC and TSV applications. 1-3 - Qiaosha Zou, Matt Poremba, Yuan Xie:
A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests. 1-7 - Daniel Nilsen Wright, Maaike M. Visser Taklo, Astrid-Sofie B. Vardøy, Helge Kristiansen:
Metal coated polymer spheres for compliant fine pitch ball grid arrays. 1-7 - Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa:
Modeling of substrate contacts in TSV-based 3D ICs. 1-4 - Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Substrate monitoring system for inspecting defects in TSV-based data buses. 1-5 - Youngwoo Kim, Jonghyun Cho, Kiyeong Kim, Heegon Kim, Joungho Kim, Srikrishna Sitaraman, Venky Sundaram, Rao R. Tummala:
Analysis and optimization of a power distribution network in 2.5D IC with glass interposer. 1-4 - Andrzej Kociubinski, M. Duk, Tomasz Bieniek, Grzegorz Janczyk, Michal Borecki:
Innovative SiC over Si photodiode based dual-band, 3D integrated detector. 1-4 - T. Robert Harris, Paul D. Franzon, W. Rhett Davis, Lee Wang:
Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits. 1-3 - Ricky Anthony, Santosh Kulkarni, Ningning Wang, Seán Cian O'Mathuna:
Advanced processing for high efficiency inductors for 2.5D/3D Power Supply in Package. 1-4 - Tomasz Bieniek, Grzegorz Janczyk, Magdalena Ekwinska, T. Budzynski, Piotr Gluszko, Piotr Grabiec, Andrzej Kociubinski:
Novel methodology for 3D MEMS-IC design and co-simulation on MEMS microphone smart system example. 1-5 - Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi:
An impact of circuit scale on the performance of 3-D stacked arithmetic units. 1-5 - Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie:
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. 1-7 - Yann Beilliard, Stéphane Moreau, Léa Di Cioccio, Perceval Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P.-H. Jouneau, E. Rolland, Thomas Signamarcheix:
Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding. 1-8
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