default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID3DIC 2011: Osaka, Japan
- Mitsumasa Koyanagi, Morihiro Kada:
2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012. IEEE 2012, ISBN 978-1-4673-2189-1 - Tadatomo Suga
, Ryuichi Kondoh:
Low temperature bonding for 3D interconnects. 1-4 - Alain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne:
Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. 1-4 - Y. H. Hu, C. S. Liu, M. J. Lii, Kenneth J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu:
3D stacking using Cu-Cu direct bonding. 1-4 - Satoru Toyoda, A. Shibata, M. Harada, Takahide Murayama, Toshiyuki Sakuishi, M. Hatanaka, Yasuhiro Morikawa, Koukou Suu:
TSV process solution for 3D-IC. 1-5 - Ryohei Sato, Akihiro Tsukada, Yukihiro Sato, Yoshiharu Iwata, Hidenori Murata, Shigenobu Sekine, Ryuji Kimura, Keijiroh Kishi:
Study on high performance and productivity of TSV's with new filling method and alloy for advanced 3D-SiP. 1-4 - Sinwoo Kang, Sungdong Cho, Kiyoung Yun, Sangwook Ji, Kisoon Bae, Woonseob Lee, Eunji Kim, Jangho Kim, Jonghoon Cho, Hyongyol Mun, Yeong L. Park:
TSV optimization for BEOL interconnection in logic process. 1-4 - Tomoji Nakamura, Hideki Kitada, Yoriko Mizushima, Nobuhide Maeda, Koji Fujimoto, Takayuki Ohba:
Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects. 1-4 - Cheng-Ta Ko, Zhi-Cheng Hsiao, Y. J. Chang, Peng-Shu Chen, J. H. Huang, Hsin-Chia Fu, Y. J. Huang, C. W. Chiang, W. L. Tsat, Y. H. Chen, Wei-Chung Lo, Kuan-Neng Chen:
Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies. 1-4 - Yuki Ohara, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. 1-4 - Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, Wenqi Zhang, Eric Beyne:
3D stacking using ultra thin dies. 1-5 - Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi:
Chip-level TSV integration for rapid prototyping of 3D system LSIs. 1-4 - Sebastien Mermoz, Loic Sanchez, Léa Di Cioccio, Jean Berthier, Emilie Deloffre, Christian Fretigny:
Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield. 1-5 - Takafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Temporary bonding strength control for self-assembly-based 3D integration. 1-4 - Xiaoyu Mi, Osamu Toyoda, Satoshi Ueda, Fumihiko Nakazawa:
A 3D heterogeneous integration method using LTCC wafer for RF applications. 1-5 - Revanth Nadipalli, Ji Fan, Holden King Ho Li, Keng Hoong Wee, Hao Yu, Chuan Seng Tan:
3D integration of MEMS and CMOS via Cu-Cu bonding with simultaneous formation of electrical, mechanical and hermetic bonds. 1-5 - Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. 1-4 - Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, H. Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi:
A very low area ADC for 3-D stacked CMOS image processing system. 1-4 - Makoto Motoyoshi, Junichi Takanohashi, Takafumi Fukushima, Yasuo Arai, Mitsumasa Koyanagi:
Stacked SOI pixel detector using versatile fine pitch μ-bump technology. 1-4 - Paul D. Franzon, W. Rhett Davis, Zheng Zhou, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapti Srinavas:
Coordinating 3D designs: Interface IP, standards or free form? 1-3 - Shivam Priyadarshi, Jianchen Hu, Won Ha Choi, Samson Melamed, Xi Chen, W. Rhett Davis, Paul D. Franzon:
Pathfinder 3D: A flow for system-level design space exploration. 1-8 - G. Druais, Pascal Ancey, C. Aumont, V. Caubet, Laurent-Luc Chapelon, C. Chaton, Séverine Cheramy, S. Cordova, E. Cirot, Jean-Philippe Colonna, Perceval Coudrain, T. Divel, Y. Dodo, Alexis Farcy, N. Guitard, K. Haxaire, Nicolas Hotellier, F. Leverd, R. Liou, Jean Michailos, A. Ostrovsky, Sebastien Petitdidier, J. Pruvost, D. Riquet, O. Robin, E. Saugier, Nicolas Sillon:
3D integration demonstration of a wireless product with design partitioning. 1-5 - Futoshi Furuta, Kenichi Osada:
6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV. 1-4 - Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne:
In-tier diagnosis of power domains in 3D TSV ICs. 1-6 - Elyse Rosenbaum, Vrashank Shukla, Min-Sun Keel:
ESD protection networks for 3D integrated circuits. 1-7 - Xin Liu, Lei Wang, Mini Jayakrishnan, Jingjing Lan, Hongyu Li, Chong Ser Choong, M. Kumarasamy Raja, Yongxin Guo, Wang Ling Goh, Jin He, Shan Gao, Minkyu Je:
A miniaturized heterogeneous wireless sensor node in 3DIC. 1-4 - Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee:
Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing. 1-8 - Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture. 1-6 - Mariappan Murugesan, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
High density Cu-TSVs and reliability issues. 1-4 - Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi:
W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress. 1-4 - Osamu Nakatsuka, Hideki Kitada, Young-Suk Kim, Yoriko Mizushima, Tomoji Nakamura, Takayuki Ohba, Shigeaki Zaima:
Characterization of local strain around trough silicon via interconnects in wafer-on-wafer structures. 1-4 - Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, Wenqi Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte:
Analysis of microbump induced stress effects in 3D stacked IC technologies. 1-5 - Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa:
Damage evaluation of wet-chemical silicon-wafer thinning process. 1-4 - Kuan-Neng Chen, Z. Xu, Fei Liu, Cheng-Ta Ko, Chuan-An Cheng, W. C. Huang, H. L. Lin, C. Cabral, Zhi-Cheng Hsiao, N. Klymko, Hsin-Chia Fu, Y. H. Chen, Jian-Qiang Lu, Wei-Chung Lo:
Cu-based bonding technology for 3D integration applications. 1-4 - Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Yuki Ohara, Tetsu Tanaka, Mitsumasa Koyanagi:
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. 1-4 - Léa Di Cioccio, Rachid Taibi, Cédrick Chappaz, Stéphane Moreau, Laurent-Luc Chapelon, Thomas Signamarcheix:
200°C direct bonding copper interconnects : Electrical results and reliability. 1-4 - Eric Beyne:
Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions. 1-6 - Deepak C. Sekar, Zvi Or-Bach:
Monolithic 3D-ICs with single crystal silicon layers. 1-2 - John H. Lau:
Recent advances and new trends in nanotechnology and 3D integration for semiconductor industry. 1-23 - Hideaki Ishihara:
Evolutional Directions of Smart Automotive Systems and Semiconductors. 1 - Dau Fatt Lim, K. C. Leong, Chuan Seng Tan:
Selection of underfill material in Cu hybrid bonding and its effect on the transistor keep-out-zone. 1-4 - Masanori Hayase, Naoki Mizukoshi, Masayuki Nagao:
Copper deep via superfilling by selective accelerator deactivation. 1-4 - Taro Hayashi, Kazuo Kondo, Minoru Takeuchi, Yushi Suzuki, Takeyasu Saito, Naoki Okamoto, Masao Marunaka, Takayuki Tsuchiya, Masaru Bunya:
3D interconnected technology by high speed copper electrodeposition using diallylamine levelers. 1-4 - Fumihiro Inoue, Harold Philipsen, Alex Radisic, Silvia Armini, Peter Leunissen, Hiroshi Miyake, Ryohei Arima, Tomohiro Shimizu, Toshiaki Ito, Hirofumi Seki, Yuko Shinozaki, Tomohiko Yamamoto, Shoso Shingubara:
Low temperature through-Si via fabrication using electroless deposition. 1-4 - Fa Xing Che, Wahyuaji Narottama Putra, A. Heryanto, A. Trigg, S. Gao, Chee Lip Gan:
Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV). 1-6 - Keith Buchanan, Dave Thomas, Hefin Griffiths, Kathrine Crook, Daniel Archard, Mark Carruthers, Masahiko Tanaka:
Plasma etch and dielectric deposition processes for TSV Reveal. 1-2 - Stephen Olson, Klaus Hummler:
TSV reveal etch for 3D integration. 1-4 - Young-Ki Ko, Myong-Suk Kang, Hiroyuki Kokawa, Yutaka S. Sato, Sehoon Yoo, Chang-Woo Lee:
Advanced TSV filling method with Sn alloy and its reliability. 1-4 - Sten Vollebregt, Ryoichi Ishihara, Johan van der Cingel, Kees Beenakker:
Low-temperature bottom-up integration of carbon nanotubes for vertical interconnects in monolithic 3D integrated circuits. 1-4 - Erik Vick, Scott H. Goodwin, Garry Cunnigham, Dorota Temple:
Vias-last process technology for thick 2.5D Si interposers. 1-4 - Nobuhide Maeda, Young-Suk Kim, Y. Hikosaka, T. Eshita, Hideki Kitada, K. Fujimoto, Yoriko Mizushima, K. Suzuki, Tadao Nakamura, Akihito Kawai, Kazuhisa Arai, Takayuki Ohba:
Development of ultra-thinning technology for logic and memory heterogeneous stack applications. 1-4 - Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda:
Void reduction in wafer bonding by simultaneously formed ventilation channels. 1-5 - Kosuke Kitaichi, Haruo Shimamoto, Chuichi Miyazaki, Yoshiyuki Abe, Sigeaki Saito, Shoji Yasunaga:
Development of high accuracy wafer thinning and pickup technology for thin wafer. 1-5 - Kazuta Saito, Richard J. Webb, Blake R. Dronen:
Advances of 3M™ wafer support system. 1-4 - Jae Hak Lee, Choong D. Yoo, Jun-Yeob Song, Seung S. Lee, Sun-Rak Kim:
A study on the edge traces technique for 3D stack chip. 1-4 - Gyujei Lee, Suk-woo Jeon, Kwang-yoo Byun, Dongil Kwon:
Mechanical characterization of residual stress around TSV through instrumented indentation algorithm. 1-6 - Kota Nakahira, Fumiaki Endo, Ryosuke Furuya, Ken Suzuki, Hideo Miura:
Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnections. 1-6 - Naoki Saito, Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura:
Mechanical and electrical reliability of copper interconnections for 3DIC. 1-6 - Toru Ikeda, Masatoshi Oka, Shinya Kawahara, Noriyuki Miyazaki, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada:
Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package. 1-6 - Sung-Hoon Choa, Haeng-Soo Lee, Kyoung-Ho Kim:
Numerical analysis of bonding process-induced deformation for 3D package. 1-5 - Taeshik Yoon, Inhwa Lee, Taek-Soo Kim:
Mechanical reliability of Cu/low-k interconnects and underfill. 1-4 - Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma, Takahiro Kinoshita, Takashi Kawakami:
Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration. 1-7 - Toshiaki Itabashi, Masashi Kotani, Melvin P. Zussman, K. Zoschke, T. Fischer, M. Topper, Hiroyuki Ishida:
High temperature bonding solutions enabling thin wafer process and handling on 3D-IC manufacturing. 1-4 - Byung-Hyun Kwak, Sung-Hyuk Kim, Young-Bae Park:
Current stressing effect on interfacial reaction characteristics of Cu pillar/Sn-3.5Ag microbumps for 3D integration. 1-2 - Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. 1-4 - Sandip Halder, Ingrid De Wolf, Alain Phommahaxay, Andy Miller, Mireille Maenhoudt, Gerald Beyer, Bart Swinnen, Eric Beyne:
In-line metrology and inspection for process control during 3D stacking of IC's. 1-4 - Fumihiko Nakazawa, Takeaki Shimanouchi, Tadashi Nakatani, Takashi Katsuki, Hisao Okuda, Osamu Toyoda, Satoshi Ueda:
Effect of frequency in the 3D integration of a PZT-actuated MEMS switch using a single crystal silicon asymmetric beam. 1-5 - H. Y. Li, L. Xie, L. G. Ong, A. Baram, I. Herer, Arnon Hirshberg, S. C. Chong, D. L. Kwong:
Ultra-compact micro-coil realized via multilevel dense TSV coil for MEMs application. 1-4 - Xiaowu Zhang, Ranjan Rajoo, F. X. Che, C. S. Selvanayagam, W. K. Choi, Shan Gao, Guo-Qiang Lo, Dim-Lee Kwong:
A low stress bond pad design optimization of low temperature solder interconnections on TSVs for MEMS applications. 1-5 - Yuka Ito, Shinsuke Terada, Shinya Arai, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi:
High-bandwidth data transmission of new transceiver module through optical interconnection. 1-4 - Akihiro Ikeda, Naoya Watanabe, Tanemasa Asano:
High frequency signal transmission characteristics of cone bump interconnections. 1-5 - Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, Tanemasa Asano:
Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration. 1-4 - P. Enquist:
Scalable direct bond technology and applications driving adoption. 1-5 - Sung-Geun Kang, Youngrae Kim, Eun-Sol Kim, Naeun Lim, Teakgyu Jeong, Jieun Lee, Sarah Eunkyung Kim, Sungdong Kim:
Evaluation of wafer level Cu bonding for 3D integration. 1-2 - Akiko Okada, Masatsugu Nimura, Naoko Unami, Akitsu Shigetou, Hirokazu Noma, Katsuyuki Sakuma, Jun Mizuno, Shuichi Shoji:
Low temperature Au-Au bonding with VUV/O3 treatment. 1-5 - Won-Myoung Ki, Myong-Suk Kang, Sehoon Yoo, Chang-Woo Lee:
Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC. 1-4 - Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka:
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 1-4 - Nam Hee Kwon, S. M. Hong, Yong-Won Cha, Sun Jae Lee, Han Gyul Lee, Areum Kim, Soo Won Kim, Chang Hyun Kim, Sung Gyu Pyo:
Effect of planarity on the 3D integration in 3-D integrated CMOS image sensor. 1-3 - Manuel Suarez, Víctor M. Brea, Fernando Pardo, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez:
A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors. 1-8 - Wei Zhou, Max Guest, Darcy Hart:
System level evaluation of Silicon imager based see-through Silicon application. 1-2 - Hans-Günther Moser, Ladislav Andricek, Michael Beimforde, G. Liemann, Anna Macchiolo, Richard Nisius, Rainer Helmut Richter, Philipp Weigell:
Development of pixel detectors for particle physics using SLID-ICV interconnection technology. 1-4 - Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A novel reconfigurable logic device base on 3D stack technology. 1-4 - Teruyoshi Hatanaka, Koh Johguchi, Ken Takeuchi:
A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives. 1-4 - Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures. 1-8 - Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki J. Murakami:
Performance evaluation of 3D stacked multi-core processors with temperature consideration. 1-5 - Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Yusuke Endo, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Effects of 3-D stacked vector cache on energy consumption. 1-6 - Mohamad Hairol Jabbar, Dominique Houzet, Omar Hammami:
3D multiprocessor with 3D NoC architecture based on Tezzaron technology. 1-5 - Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda:
PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. 1-2 - Omar Hammami, A. M'zah, Khawla Hamwi:
Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration. 1-4 - Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke:
3D floorplanning considering vertically aligned rectilinear modules using T∗-tree. 1-5 - Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto:
A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. 1-6 - Chao Zhang, Guangyu Sun:
Fabrication cost analysis for 2D, 2.5D, and 3D IC designs. 1-4 - Seyyed Hasan Moallempour, Seyyed Ahmad Razavi, Morteza Saheb Zamani:
TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication. 1-5 - Farhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki J. Murakami:
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. 1-4 - Andy Heinig, Christoph Sohrmann:
Multi-step approach for thermal optimization of 3D-IC and package. 1-5 - Xiongfei Liao, Jun Zhou, Xin Liu:
Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCs. 1-4 - Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila:
HIBS - Novel inter-layer bus structure for stacked architectures. 1-7 - Hong-Yeol Lim, Gi-Ho Park:
Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology. 1-5 - Joseph Romen Cubillo, Roshan Weerasekera, Zaw Zaw Oo, En-Xiao Liu, Bob Conn, Surya Bhattacharya, Robert Patti:
Interconnect design and analysis for Through Silicon Interposers (TSIs). 1-6 - Tao Zhang, Guangyu Sun:
Using NEM relay to improve 3DIC cost efficiency. 1-4 - Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume:
A built-in test circuit for open defects at interconnects between dies in 3D ICs. 1-5 - Brandon Noia, Krishnendu Chakrabarty:
Pre-bond testing of die logic and TSVs in high performance 3D-SICs. 1-5 - Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur:
3D-Scalable Adaptive Scan (3D-SAS). 1-6 - Thomas Whipple, Thad McCracken:
Silicon interposer request-for-quote IC-package Co-design flow. 1-7 - Katsuyuki Ikeuchi, Makoto Takamiya, Takayasu Sakurai:
Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies. 1-5 - Myat Thu Linn Aung, Eric Teck Heng Lim, Takefumi Yoshikawa, Tony Tae-Hyoung Kim:
Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC. 1-4 - Yuhao Wang, Chun Zhang, Revanth Nadipalli, Hao Yu, Roshan Weerasekera:
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar. 1-6 - Ran Wang, Gary Charles, Paul D. Franzon:
Modeling and compare of through-silicon-via (TSV) in high frequency. 1-6 - A. Ege Engin, N. Srinidhi Raghavan:
Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:22 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
