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ORCIDCICC 2005: San Jose, California, USA
- Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005. IEEE 2005, ISBN 0-7803-9023-7
- Trudy Stetzler:
Welcome and opening remarks. 1 - Jim Lipman, Albert Z. Wang:
Body wellness without wires. 2-3 - Mohamad Sawan, Yamu Hu, Jonathan Coulombe:
Wirelessly powered and bidirectional data exchanged in smart medical microsystems. 5-12 - Bert Gyselinckx, Chris Van Hoof
, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov:
Human++: autonomous wireless sensors for body area networks. 13-19 - Gordon W. Roberts, Robert C. Aitken:
Noise and reliability containment approaches. 20-21 - David J. Leavins, Kee Sup Kim, Subhasish Mitra, Eddie J. Rodriguez:
Robust platform design in advanced VLSI technologies. 23-30 - Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa:
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. 31-34 - Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata:
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. 35-38 - Chaiyuth Chansungsan:
Auto-referenced on-die power supply noise measurement circuit. 39-42 - Thomas Zimmermann, Aurangzeb Khan:
Real-world SoC design methods and applications. 42-43 - Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. 45-49 - Toshiki Takeuchi, Hiroyuki Igura, Takeshi Hashimoto, Soichi Tsumura, Naoki Nishi:
Scalable bus interface for HSDPA co-processor extension. 51-54 - Yanmei Li, Fernando De Bernardinis, Brian P. Otis, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
A low-power mixed-signal baseband system design for wireless sensor networks. 55-58 - S. Sriram, Kathy Brown, Raphael Defosseux, Filip Moerman, Olivier Paviot, V. Sundararajan, Alan Gatherer:
A 64 channel programmable receiver chip for 3G wireless infrastructure. 59-62 - Amir Hekmatpour, Charles Alley, Brian Stempel, James Coulter, Azadeh Salehi, Arash Shafie, Chloe Palenchar:
A heterogeneous functional verification platform. 63-66 - Lawrence Clark, Masataka Matsui:
DSP for wireless. 66-67 - Alireza Tarighat, Eugene Grayver, Ahmed M. Eltawil, Jean-François Frigon, Gennady Y. Poberezhskiy, Hanli Zou, Babak Daneshrad:
A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilities. 69-72 - Ahmed M. Eltawil, Eugene Grayver, Alireza Tarighat, Jean-François Frigon, Aliazam Abbasfar:
Implementation of a digital timing recovery circuit for CDMA applications. 73-76 - Khurram Muhammad, Imtinan Elahi, Tom Jung:
A low-area decimation filter for ultra-high speed 1-bit ΣΔ A/D converters. 77-80 - Yunho Jung, Jiho Kim, Seungphyo Noh, Hongil Yoon, Jaeseok Kim:
A digital 120Mb/s MIMO-OFDM baseband processor for high speed wireless LANs. 81-84 - Ann Marie Rincon, Kris Iniewski:
Emerging technologies for unique applications. 84-85 - Charles T. Black:
Integration of self assembly for semiconductor microelectronics. 87-91 - Sitaraman V. Iyer, Hasnain Lakdawala, Rajarishi S. Sinha, Eric J. Zacherl, Richard T. Unetich, Daniel M. Gaugel, David F. Guillou, L. Richard Carley:
A 0.5 mm2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor. 93-96 - Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo:
Electric power generation using piezoelectric resonator for power-free sensor node. 97-100 - Alberto Fazzi, Luca Magagni, Mauro Mirandola, Roberto Canegallo, Stefan Schmitz, Roberto Guerrieri:
A 0.14mW/Gbps high-density capacitive interface for 3D system integration. 101-104 - Ran Li, Xiaoling Guo, Dong-Jun Yang, Kenneth K. O:
Initialization of a wireless clock distribution system using an external antenna. 105-108 - Amjad Obeidat, Eric Naviasky:
Circuits and systems for high-speed links. 108-109 - Sorin P. Voinigescu, Timothy O. Dickson, Theodoros Chalvatzis, Altan Hazneci, Ekaterina Laskin, Rudy Beerkens, Imran Khalid, Edward S. Rogers Sr.:
Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes. 111-118 - Tai-Yuan Chen, Jun-Chau Chien, Liang-Hung Lu:
A 45.6-GHz matrix distributed amplifier in 0.18-nm CMOS. 119-122 - John W. Fattaruso, Benjamin Sheahan:
A 3V, 4.25Gb/s laser driver with 0.4V output voltage compliance. 123-126 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA 10.7GHz SiGe BICMOS limiting amplifier using multiple offset cancellation loops. 127-130
- Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura:
A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. 131-134 - Jinghong Chen, Fadi Saibi, Eduard Säckinger, Kamran Azadet, Joe Othmer, Mark Yu, Fuji Yang, Jenshan Lin, Titus Huang, Tingping Liu:
An integrated CMOS transceiver for a 40Gb/s SCM optical communication system. 135-138 - Ranjit Gharpurey, Stefan Drude:
Ultra wideband circuits and transceivers. 138-139 - Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Ran-Hong Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee:
Multiband UWB transceivers. 141-148 - Sudhir Aggarwal, Domine Leenaerts, Remco van de Beek, Gerard van der Weide, Harish Kundur, Jos Bergervoet, Alan L. Landesman, Yifeng Zhang, Charles J. Razzell, Helen Waite, Raf Roovers:
A low power implementation for the transmit path of a UWB transceiver. 149-152 - Fred S. Lee, Anantha P. Chandrakasan:
A BiCMOS ultra-wideband 3.1-10.6GHz front-end. 153-156 - Giuseppe Cusmai, Massimo Brandolini, Paolo Rossi, Francesco Svelto:
An interference robust 0.18μm CMOS 3.1-8GHz receiver front-end for UWB radio. 157-160 - Chih-Fan Liao, Shen-Iuan Liu:
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver. 161-164 - Yorgos Palaskas, Ralph E. Bishop, Ashoke Ravi, Krishnamurthy Soumyanath:
A 90-nm MOS-only 3-11GHz transmitter for UWB. 165-168 - Steven J. E. Wilton, Albert Stritter:
Advances in programmable logic. 168-169 - Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Two-stage physical synthesis for FPGAs. 171-178 - Victor O. Aken'Ova, Guy Lemieux, Resve A. Saleh:
An improved "soft" eFPGA design and implementation strategy. 179-182 - Arifur Rahman, Satyaki Das, Tim Tuan, Anirban Rahut:
Heterogeneous routing architecture for low-power FPGA fabric. 183-186 - Navid Azizi, Farid N. Najm:
Look-up table leakage reduction for FPGAs. 187-190 - David Varghese, J. Neil Ross:
A continuous-time hierarchical field programmable analogue array. 191-194 - Larry Wissel:
Poster session. 194-195 - Jun-Gi Jo, Changsik Yoo, Chun-Seok Jeong, Chan-Young Jeong, Mi-Young Lee, Jong-Kee Kwon:
A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology. 195-198 - Kai Di Feng, Jui-Chu Lee:
Spark current in charge pump of phase lock loop. 199-202 - Rui Yu, Yong Ping Xu:
A 47.3-MHz SAW resonator based CMOS second-order bandpass sigma-delta modulator with 54-dB peak SNDR. 203-206 - Soon-Kyun Shin, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun, Jae-Whui Kim:
A high current driving charge pump with current regulation method. 207-210 - Francis D. Braun, David W. Parent, Tamara A. Papalias:
On-chip temperature control circuit using common devices. 215-218 - Kyle R. Wissmiller, Jonathan E. Knudsen, Travis J. Alward, Zi P. Li, David R. Allee, Lawrence T. Clark:
Reducing power in flexible a-Si digital circuits while preserving state. 219-222 - Amine Bermak:
An 8/4-bit reconfigurable digital pixel array with on-chip non-uniform quantizer. 223-226 - Rajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob:
A high performance, high voltage output buffer in a low voltage CMOS process. 227-230 - Soon-Kyun Shin, Wang Yu, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun, Jae-Whui Kim:
A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature. 231-234 - Tom Beacom, Timothy C. Buchholtz, D. Bradley, Jack Randolph, Salvatore N. Storino, Mark Veldhuizen, Sherman M. Dance, Jente B. Kuang, Steve Schwinn, Sue Cox, Fred Ziegler, J. Kao, Chuck Li, Christophe Tretz, J. Cabellon, Andrew Freemyer, Matthew Tubbs:
Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor. 235-238 - Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. 239-242 - Saied Hemati, Amir H. Banihashemi, Calvin Plett:
An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32, 8, 10) LDPC code. 243-246 - Hanpei Koike, Toshihiro Sekigawa:
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together. 247-250 - John Danson, Calvin Plett, Niall Tait:
Design and characterization of a MEMS capacitive switch for improved RF amplifier circuits. 251-254 - ByungJun Min, Kang-Woon Lee, Han-Ju Lee, So-Ra Kim, Seung-Gyu Oh, Byung-Gil Jeon, Hee-Hyun Yang, Min-Kyu Kim, Sung-Hee Cho, Honsik Cheong, Chilhee Chung, Kinam Kim:
An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards. 255-258 - Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa:
A 333MHz random cycle DRAM using the floating body cell. 259-262 - Johannes Fellner:
A one time programming cell using more than two resistance levels of a polyfuse. 263-266 - Troy Ruud, Zhongmin Li, Rich Friel, Bryce Rasmussen, Shan Mo:
An overview of structured digital ASIC XPressArray©-II I/O. 267-270 - Seongmo Park, Hanjin Cho, Heebum Jung, Dukdong Lee:
An implemented of H.264 video decoder using hardware and software. 271-275 - Arthur Nieuwoudt, Michael S. McCorquodale, Ruba T. Borno, Yehia Massoud:
Efficient analytical modeling techniques for rapid integrated spiral inductor prototyping. 281-284 - Wei-Zen Chen, Kuo-Ching Hsu:
Miniaturized 3-dimensional transformer design. 285-288 - Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. 289-292 - Jongrit Lerdworatawee, Won Namgoong:
Generalized noise analysis of active mixers by simple linear periodic time-varying circuit model. 293-296 - S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski:
Behavioral test benches for digital clock and data recovery circuits using Verilog-A. 297-300 - Ja Chun Ku, Maged Ghoneima, Yehea I. Ismail:
The importance of including thermal effects in estimating the effectiveness of power reduction techniques. 301-304 - Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Measurement and analysis of delay variation due to inductive coupling. 305-308 - Xiaoning Qi, Sam C. Lo, Yansheng Luo, Alex Gyure, Mahmoud Shahram, Kishore Singhal:
Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations. 309-312 - Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail:
Low-power prediction based data transfer architecture. 313-316 - Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel:
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. 317-320 - Poki Chen, Jia-Chi Zheng, Chun-Chi Chen:
A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration. 321-324 - Byung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae-Woo Lee:
A 500MHz DLL with second order duty cycle corrector for low jitter. 325-328 - Joohwan Park, Franco Maloberti:
Fractional-N PLL with 90° phase shift lock and active switched-capacitor loop filter. 329-332 - Day-Uei Li, Li-Ren Huang, Chia-Ming Tsai:
10 Gb/s CMOS laser driver with 3.3 Vpp output swing. 333-336 - Payam Heydari, Denis Lin:
A performance optimized CMOS distributed LNA for UWB receivers. 337-340 - Rola A. Baki, Mourad N. El-Gamal:
Robust multi-GHz (7.4GHz) on-chip image rejection in CMOS. 341-344 - Masato Koutani, Kunihiko Iizuka:
A high OIP3 quadrature mixer using cross-coupled transconductor. 345-348 - See Taur Lee, Solti Peng:
A GSM receiver front-end in 65 nm digital CMOS process. 349-352 - Weinan Gao, Kendal Hess, Ray Rosik, Mark Santini, Mats Lindstrom, Jason McFee, Jacek Czajka:
A Integrated Dual Direct-Conversion Tuner Chip for Digital Satellite Application. 346-349 - Hamid Rafati, Behzad Razavi:
A new receiver architecture for multiple-antenna systems. 357-360 - Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. 361-364 - Wei-Chia Zhan, Chien-Nan Kuo, Jyh-Chyurn Guo:
Low-power and high-linearity mixer design using complex transconductance equivalent circuit. 365-368 - Kostas Pagiamtzis, Ali Sheikholeslami:
Using cache to reduce power in content-addressable memories (CAMs). 369-372 - Kathleen Philips, David G. Nairn:
Data converters. 366-367 - Yun Chiu, Borivoje Nikolic, Paul R. Gray:
Scaling of analog-to-digital converters into ultra-deep-submicron CMOS. 375-382 - Ara Bicakci, Gurjinder Singh:
A ΔΣ DAC with reduced activity data weighted averaging and anti-jitter digital filter. 383-386 - Louis Luh, Willie Ng, Joseph F. Jensen, Duc Le, David L. Persechini, Stephen Thomas III, Charles H. Fields, James Lin:
A 10.24GSPS photonic sampled bandpass ΔΣ modulator direct-sampling at 12GHz. 387-390 - Ahmed M. A. Ali, Christopher Dillon, Robert Sneed, Andrew S. Morgan, John Kornblum, Lu Wu, Scott Bardsley:
A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter. 391-394 - Hirotomo Ishii, Ken Tanabe, Tetsuya Iida:
A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS. 395-398 - Jie Yuan, Nabil H. Farhat, Jan Van der Spiegel:
A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration. 399-402 - Brian P. Ginsburg, Anantha P. Chandrakasan:
Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications. 403-406 - Shahriar Mirabbasi, Cormac O'Connell:
High-speed wave-shaping techniques. 400-401 - James F. Buckwalter, Ali Hajimiri:
Crosstalk-induced jitter equalization. 409-412 - Xiaofeng Lin, Hoi Lee, Jin Liu:
A continuous-time adaptive FIR equalizer with LNV-AIL delay line for 2.5Gb/s data communication. 413-416 - Jonathan Sewter, Anthony Chan Carusone:
A 40 Gb/s transversal filter in 0.18 μm CMOS using distributed amplifiers. 417-420 - Takashi Akioka, Jean-Christophe Vial:
Memory circuits and technology. 414-415 - Kinam Kim, Gitae Jeong, Hongsik Jeong, Sungyung Lee:
Emerging memory technologies. 423-426 - Jarrod Eliason, Sudhir Madan, Hugh P. McAdams, Glen Fox, Ted Moise, Changgui Lin, Kurt Schwartz, Jim Gallia, Edwin Jabillo, Bill Kraus, Scott R. Summerfelt:
An 8Mb 1T1C ferroelectric memory with zero cancellation and micro-granularity redundancy. 427-430 - Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa:
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. 431-434 - Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A capacitorless twin-transistor random access memory (TTRAM) on SOI. 435-438 - Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy:
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. 439-442 - Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane:
Programmable techniques for cell stability test and debug in embedded SRAMs. 443-446 - Igor Arsovski, Rahul Nadkarni:
Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines. 447-450 - Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto:
A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. 451-454 - Steffen Rochel, Hidetoshi Onodera:
Substrate and phase noise characterization. 448-449 - Asad A. Abidi, Sohrab Samadian:
Phase noise in inverter-based & differential CMOS ring oscillators. 457-460 - Xiaolue Lai, Jaijeet Roychowdhury:
oder: http: //potol.eecs.berkeley.edu/~jr Analytical equations for predicting injection locking in LC and ring oscillators. 461-464 - Xiaochun Duan, Kartikeya Mayaram:
A multiple-probe approach for robust frequency domain ring oscillator simulation. 465-468 - Hai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton:
Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes. 469-472 - Nisha Checka, Anantha P. Chandrakasan, Rafael Reif:
Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL. 473-476 - Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Substrate noise immune design of an LC-tank VCO using sensitivity functions. 477-480 - Mike Zachariah, Robert C. Aitken:
ESD implementation strategies. 474-475