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"A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in ..."

Jan Craninckx, Geert Van der Plas (2007)

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DOI: 10.1109/ISSCC.2007.373386

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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  - conf/isscc/CraninckxP07
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  - https://dblp.org/rec/conf/isscc/CraninckxP07
Jan Craninckx, Geert Van der Plas:
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. ISSCC 2007: 246-600

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