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2010 – 2019
- 2019
[c17]Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic:
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC 2019: 1-4- [c16]Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst:
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. AICAS 2019: 6-10 - [c15]Timon Evenblij, Christian Tenllado, Manu Perumkunnil, Francky Catthoor, Sushil Sakhare, Peter Debacker, Gouri Sankar Kar, Arnaud Furnémont, Nicolas Bueno, José Ignacio Gómez Pérez:
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. ICCD 2019: 255-263 - [c14]Jonas Doevenspeck, Robin Degraeve, Andrea Fantini, Peter Debacker, Diederik Verkest, Rudy Lauwereins, Wim Dehaene:
Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications. IRPS 2019: 1-6 - [i1]Bram-Ernst Verhoef, Nathan Laubeuf, Stefan Cosemans, Peter Debacker, Ioannis Papistas, Arindam Mallik, Diederik Verkest:
FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. CoRR abs/1912.09356 (2019) - 2017
- [j3]Peter Debacker, Kwangsoo Han
, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1075-1088 (2017) - [c13]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC 2017: 51:1-51:6 - [c12]Luca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan:
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. ICCAD 2017: 89-94 - [c11]Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan:
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD 2017: 415-418 - 2016
- [j2]Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre:
Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications. J. Signal Process. Syst. 84(3): 413-424 (2016) - [c10]Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. ACM Great Lakes Symposium on VLSI 2016: 373-376 - [c9]Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim:
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? ICCAD 2016: 87 - [c8]Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim:
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. ISLPED 2016: 76-81 - [c7]Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean:
5nm: Has the time for a device change come? ISQED 2016: 275-277 - 2015
- [c6]Meng Li, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, Steven Dupont, Peter Debacker, Andy Dewilde, Yanxiang Huang, Liesbet Van der Perre, Wim Van Thillo:
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. A-SSCC 2015: 1-5 - 2014
- [c5]Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre:
Computation-skip error resilient scheme for recursive CORDIC. SiPS 2014: 50-55 - 2013
- [c4]Min Li, Amir Amin, Raf Appeltans, Andy Folens, Ubaid Ahmad, Hans Cappelle, Peter Debacker, Lieven Hollevoet, André Bourdoux, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre:
A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited). GlobalSIP 2013: 1222-1225 - [c3]Meng Li, Frederik Naessens, Min Li, Peter Debacker, Claude Desset, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre:
A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication. GlobalSIP 2013: 1254-1257 - [c2]Meng Li, Frederik Naessens, Peter Debacker, Praveen Raghavan, Claude Desset, Min Li, Antoine Dejonghe, Liesbet Van der Perre:
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard. SiPS 2013: 112-117 - 2012
- [j1]Martin Palkovic, Peter Debacker, Prabhat Avasare, Steven Dupont, Tom Vander Aa:
Power Estimation at Different Abstraction Levels for Wireless Baseband Processors. J. Low Power Electron. 8(5): 726-738 (2012)
2000 – 2009
- 2009
- [c1]Huub Tubbax, Johan Wouters, Jan Olbrechts, Peter Debacker, Peter Spiessens, Frederic Stubbe, Johan Danneels:
A novel positioning technique for the 2.4GHz ISM band. WPNC 2009: 145-150
Coauthor Index
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