
Rakesh Kumar 0002
Person information
- affiliation: University of Illinois at Urbana-Champaign, IL, USA
- affiliation (PhD 2006): University of California, San Diego, USA
- not to be confused with: Rakesh Kumar 0003
Other persons with the same name
- Rakesh Kumar — disambiguation page
- Rakesh Kumar 0001 (aka: Rakesh "Teddy" Kumar) — SRI International, Center for Vision Technologies, Princeton, NJ, USA
- Rakesh Kumar 0003 — Norwegian University of Science and Technology (NTNU), Trondheim, Norway (and 1 more)
- Rakesh Kumar 0004
— Indraprastha University, University School of Information, Communication and Technology, New Delhi, India
- Rakesh Kumar 0005 — Massachusetts Institute of Technology, Cambridge, USA
- Rakesh Kumar 0006
— Tata Institute of Fundamental Research, Centre For Applicable Mathematics, Bangalore, India (and 1 more)
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2020 – today
- 2020
- [j23]Saptadeep Pal
, Daniel Petrisko, Rakesh Kumar, Puneet Gupta:
Design Space Exploration for Chiplet-Assembly-Based Processors. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1062-1073 (2020) - [c64]Adam Auten, Matthew Tomei, Rakesh Kumar:
Hardware Acceleration of Graph Neural Networks. DAC 2020: 1-6 - [c63]Muhammad Husnain Mubarik, Dennis D. Weller, Nathaniel Bleier, Matthew Tomei, Jasmin Aghassi-Hagmann, Mehdi B. Tahoori, Rakesh Kumar:
Printed Machine Learning Classifiers. MICRO 2020: 73-87
2010 – 2019
- 2019
- [c62]Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar:
Architecting Waferscale Processors - A GPU Case Study. HPCA 2019: 250-263 - [c61]Matthew Tomei, Alexander G. Schwing, Satish Narayanasamy, Rakesh Kumar:
Sensor Training Data Reduction for Autonomous Vehicles. HotEdgeVideo@MOBICOM 2019: 45-50 - 2018
- [j22]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints. IEEE Micro 38(3): 32-39 (2018) - [c60]Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar:
A Case for Packageless Processors. HPCA 2018: 466-479 - [c59]Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte
, Pavan Kumar Hanumolu, Rakesh Kumar:
Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA 2018: 561-574 - 2017
- [j21]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors. ACM Trans. Comput. Syst. 35(3): 9:1-9:33 (2017) - [c58]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors. ASPLOS 2017: 3-16 - [c57]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Enabling Effective Module-Oblivious Power Gating for Embedded Processors. HPCA 2017: 157-168 - [c56]Xun Jian
, Pavan Kumar Hanumolu, Rakesh Kumar:
Understanding and Optimizing Power Consumption in Memory Networks. HPCA 2017: 229-240 - [c55]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Bespoke Processors for Applications with Ultra-low Area and Power Constraints. ISCA 2017: 41-54 - [c54]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Software-based gate-level information flow security for IoT systems. MICRO 2017: 328-340 - 2016
- [c53]Matthew Vilim, Henry Duwe, Rakesh Kumar:
Approximate bitcoin mining. DAC 2016: 97:1-97:6 - [c52]Frederic Sala, Henry Duwe, Lara Dolecek, Rakesh Kumar:
A Unified Framework for Error Correction in On-chip Memories. DSN Workshops 2016: 268-274 - [c51]Xun Jian
, Vilas Sridharan, Rakesh Kumar:
Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems. HPCA 2016: 555-567 - [c50]Henry Duwe, Xun Jian
, Daniel Petrisko, Rakesh Kumar:
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation. ISCA 2016: 634-644 - [c49]Hari Cherupalli, Rakesh Kumar, John Sartori:
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems. ISCA 2016: 671-681 - [c48]Matthew Tomei, Henry Duwe, Nam Sung Kim, Rakesh Kumar:
Bit Serializing a Microprocessor for Ultra-low-power. ISLPED 2016: 200-205 - 2015
- [j20]Lucas Francisco Wanner, Liangzhen Lai, Abbas Rahimi, Mark Gottscho, Pietro Mercati, Chu-Hsiang Huang, Frederic Sala, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt
, Puneet Gupta, Rajesh K. Gupta, Ranjit Jhala, Rakesh Kumar, Sorin Lerner, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester, Yuanyuan Zhou:
NSF expedition on variability-aware software: Recent results and contributions. it Inf. Technol. 57(3): 181-198 (2015) - [c47]Henry Duwe, Xun Jian
, Rakesh Kumar:
Correction prediction: Reducing error correction latency for on-chip memories. HPCA 2015: 463-475 - 2014
- [j19]Jason Cong, Henry Duwe, Rakesh Kumar, Sen Li:
Better-Than-Worst-Case Design: Progress and Opportunities. J. Comput. Sci. Technol. 29(4): 656-663 (2014) - [c46]John Sartori, Rakesh Kumar:
Software canaries: software-based path delay fault testing for variation-aware energy-efficient design. ISLPED 2014: 159-164 - [c45]Xun Jian
, Rakesh Kumar:
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems. SC 2014: 1035-1046 - 2013
- [j18]Xun Jian, John Sartori, Henry Duwe, Rakesh Kumar:
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity. IEEE Comput. Archit. Lett. 12(2): 39-42 (2013) - [j17]Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt
, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava
, Steven Swanson, Dennis Sylvester:
Underdesigned and Opportunistic Computing in Presence of Hardware Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 8-23 (2013) - [j16]John Sartori, Rakesh Kumar:
Exploiting Timing Error Resilience in Processor Architecture. ACM Trans. Embed. Comput. Syst. 12(2s): 89:1-89:25 (2013) - [j15]John Sartori, Rakesh Kumar:
Branch and Data Herding: Reducing Control and Memory Divergence for Error-Tolerant GPU Applications. IEEE Trans. Multim. 15(2): 279-290 (2013) - [j14]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Enhancing the Efficiency of Energy-Constrained DVFS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1769-1782 (2013) - [c44]Biplab Deka, Alex A. Birklykke, Henry Duwe, Vikash K. Mansinghka, Rakesh Kumar:
Markov chain algorithms: A template for building future robust low power systems. ACSSC 2013: 118-125 - [c43]Joseph Sloan, Rakesh Kumar, Greg Bronevetsky:
An algorithmic approach to error localization and partial recomputation for low-overhead fault tolerance. DSN 2013: 1-12 - [c42]Xun Jian
, Rakesh Kumar:
Adaptive Reliability Chipkill Correct (ARCC). HPCA 2013: 270-281 - [c41]Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Statistical analysis and modeling for error composition in approximate computation circuits. ICCD 2013: 47-53 - [c40]Xun Jian, Nathan DeBardeleben, Sean Blanchard, Vilas Sridharan, Rakesh Kumar:
Analyzing Reliability of Memory Sub-systems with Double-Chipkill Detect/Correct. PRDC 2013: 88-97 - [c39]Xun Jian
, Henry Duwe, John Sartori, Vilas Sridharan, Rakesh Kumar:
Low-power, low-storage-overhead chipkill correct via multi-line error correction. SC 2013: 24:1-24:12 - 2012
- [j13]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 404-417 (2012) - [c38]John Sartori, Rakesh Kumar:
Branch and data herding: reducing control and memory divergence for error-tolerant GPU applications. PACT 2012: 427-428 - [c37]Joseph Sloan, John Sartori, Rakesh Kumar:
On software design for stochastic processors. DAC 2012: 918-923 - [c36]John Sartori, Rakesh Kumar:
Compiling for energy efficiency on timing speculative processors. DAC 2012: 1301-1308 - [c35]Joseph Sloan, Rakesh Kumar, Greg Bronevetsky:
Algorithmic approaches to low overhead fault detection for sparse linear algebra. DSN 2012: 1-12 - [c34]John Sartori, Ben Ahrens, Rakesh Kumar:
Power balanced pipelines. HPCA 2012: 261-272 - 2011
- [j12]John Sartori, Rakesh Kumar:
Stochastic Computing. Found. Trends Electron. Des. Autom. 5(3): 153-210 (2011) - [j11]Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar:
MOPED: Accelerating Data Communication on Future CMPs. IEEE Micro 31(4): 42-50 (2011) - [c33]John Sartori, Rakesh Kumar:
Architecting processors to allow voltage/reliability tradeoffs. CASES 2011: 115-124 - [c32]John Sartori, Joseph Sloan, Rakesh Kumar:
Stochastic computing: embracing errors in architectureand design of processors and applications. CASES 2011: 135-144 - [c31]Tuck-Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar:
On the efficacy of NBTI mitigation techniques. DATE 2011: 932-937 - [c30]Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun:
MOPED: Orchestrating interprocess message data on CMPs. HPCA 2011: 111-120 - [c29]David Kesler, Biplab Deka, Rakesh Kumar:
A hardware acceleration technique for gradient descent and conjugate gradient. SASP 2011: 94-101 - [p1]Rakesh Kumar, Timothy G. Mattson, Gilles Pokam, Rob F. Van der Wijngaart:
The Case for Message Passing on Many-Core Chips. Multiprocessor System-on-Chip 2011: 115-123 - 2010
- [j10]Shoaib Akram, Alexandros Papakonstantinou, Rakesh Kumar, Deming Chen:
A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. Int. J. Reconfigurable Comput. 2010: 205852:1-205852:22 (2010) - [c28]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC 2010: 825-831 - [c27]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC 2010: 825-830 - [c26]Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones:
Stochastic computation. DAC 2010: 859-864 - [c25]Sriram Narayanan, John Sartori, Rakesh Kumar, Douglas L. Jones:
Scalable stochastic processors. DATE 2010: 335-338 - [c24]Joseph Sloan, David Kesler, Rakesh Kumar, Ali Rahimi:
A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. DSN 2010: 161-170 - [c23]John Sartori, Rakesh Kumar:
Overscaling-friendly timing speculation architectures. ACM Great Lakes Symposium on VLSI 2010: 209-214 - [c22]John Sartori, Rakesh Kumar:
Low-Overhead, High-Speed Multi-core Barrier Synchronization. HiPEAC 2010: 18-34 - [c21]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA 2010: 1-11 - [c20]Nicolas Zea, John Sartori, Ben Ahrens, Rakesh Kumar:
Optimal power/performance pipelining for error resilient processors. ICCD 2010: 356-363 - [c19]John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta:
Variation-aware speed binning of multi-core processors. ISQED 2010: 307-314
2000 – 2009
- 2009
- [j9]Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08). SIGARCH Comput. Archit. News 37(2): 1 (2009) - [c18]Joseph Sloan, Rakesh Kumar:
Towards scalable reliability frameworks for error prone CMPs. CASES 2009: 261-270 - [c17]John Sartori, Rakesh Kumar:
Distributed peak power management for many-core architectures. DATE 2009: 1556-1559 - [c16]John Sartori, Rakesh Kumar:
Three scalable approaches to improving many-core throughput for a given peak power budget. HiPC 2009: 89-98 - [c15]Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou:
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS 2009: 129 - [c14]Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar:
Reducing peak power with a table-driven adaptive processor core. MICRO 2009: 189-200 - [c13]Shoaib Akram, Rakesh Kumar, Deming Chen:
Workload adaptive shared memory multicore processors with reconfigurable interconnects. SASP 2009: 7-14 - 2008
- [j8]Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07). SIGARCH Comput. Archit. News 36(2): 1 (2008) - [j7]Nicolas Zea, John Sartori, Rakesh Kumar:
Servo: a programming model for many-core computing. SIGARCH Comput. Archit. News 36(2): 28-37 (2008) - 2007
- [j6]Rakesh Kumar, Dean M. Tullsen:
The architecture of Efficient Multi-Core Processors: A Holistic Approach. Adv. Comput. 69: 1-87 (2007) - [j5]Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi:
Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06). SIGARCH Comput. Archit. News 35(1): 2 (2007) - [c12]Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen:
Proximity-aware directory-based coherence for multi-core processor architectures. SPAA 2007: 126-134 - 2006
- [b1]Rakesh Kumar:
Holistic design for multi-core architectures. University of California, San Diego, USA, 2006 - [c11]Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi:
Core architecture optimization for heterogeneous chip multiprocessors. PACT 2006: 23-32 - [c10]David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen:
Application-specific customization of parameterized FPGA soft-core processors. ICCAD 2006: 261-268 - [c9]David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky:
Conjoining soft-core FPGA processors. ICCAD 2006: 694-701 - [c8]M. De Vuyst, Rakesh Kumar, Dean M. Tullsen:
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors. IPDPS 2006 - 2005
- [j4]Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou:
The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. IEEE Comput. Archit. Lett. 4(1): 1 (2005) - [j3]Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan:
Heterogeneous Chip Multiprocessors. Computer 38(11): 32-38 (2005) - [j2]Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). SIGARCH Comput. Archit. News 33(4): 4 (2005) - [c7]Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen:
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. ISCA 2005: 408-419 - 2004
- [c6]Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas:
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. ISCA 2004: 64-75 - [c5]Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder:
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy. MICRO 2004: 183-194 - [c4]Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen:
Conjoined-Core Chip Multiprocessing. MICRO 2004: 195-206 - 2003
- [j1]Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen:
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. IEEE Comput. Archit. Lett. 2 (2003) - [c3]Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen:
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. MICRO 2003: 81-92 - 2002
- [c2]Rakesh Kumar, Tusar Kanti Patra, Anupam Basu:
Software Energy Optimization of Real Time Preemptive Tasks by Minimizing Cache-Related Preemption Costs. ISHPC 2002: 321-328 - [c1]Rakesh Kumar, Dean M. Tullsen:
Compiling for instruction cache performance on a multithreaded architecture. MICRO 2002: 419-429
Coauthor Index

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