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ORCIDDinesh Pamunuwa
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2020 – today
- 2024
[c30]Elliott Worsey, Qi Tang, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Dinesh Pamunuwa
:
Nanoelectromechanical analog-to-digital converter for low power and harsh environments. ISCAS 2024: 1-5
2010 – 2019
- 2018
- [j8]Tian Qin, Simon J. Bleiker, Sunil Rana, Frank Niklaus, Dinesh Pamunuwa:
Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays. IEEE Access 6: 15997-16009 (2018) - 2015
- [j7]Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa:
Zero-load predictive model for performance analysis in deflection routing NoCs. Microprocess. Microsystems 39(8): 634-647 (2015) - [c29]Tian Qin, Sunil Rana, Dinesh Pamunuwa:
Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits. ICCAD 2015: 641-648 - 2014
- [j6]Sunil Rana, Tian Qin, Antonios Bazigos, Daniel Grogg, Michel Despont, Christopher Lawrence Ayala, Christoph Hagleitner, Adrian Mihai Ionescu, Roberto Canegallo, Dinesh Pamunuwa:
Energy and Latency Optimization in NEM Relay-Based Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2348-2359 (2014) - 2013
- [c28]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen:
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. 3DIC 2013: 1-5 - [c27]Sunil Rana, Tian Qin, Dinesh Pamunuwa, Daniel Grogg, Michel Despont, Yu Pu, Christoph Hagleitner:
Modelling NEM relays for digital circuit applications. ISCAS 2013: 805-808 - 2011
- [c26]Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa:
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317 - [c25]Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion:
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS 2011: 57-64 - [c24]Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch:
3-D integration and the limits of silicon computation. VLSI-SoC 2011: 343-348 - [p1]Axel Jantsch, Matthew Grange, Dinesh Pamunuwa:
The Promises and Limitations of 3-D Integration. 3D Integration for NoC-based SoC Architectures 2011: 27-44 - 2010
- [c23]Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen:
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE 2010: 1325-1328
2000 – 2009
- 2009
- [j5]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1237-1250 (2009) - [c22]Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen:
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7 - [c21]Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng:
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC 2009: 1-8 - [c20]Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert:
Design of Robust Molecular Electronic Circuits. ISCAS 2009: 1819-1822 - [c19]Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert:
Designing Reliable Digital Molecular Electronic Circuits. NanoNet 2009: 111-115 - [c18]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen:
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123 - 2008
- [j4]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 589-593 (2008) - [c17]Dinesh Pamunuwa:
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. DATE 2008: 1126-1127 - [c16]Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert:
Application of Molecular Electronics Devices in Digital Circuit Design. NanoNet 2008: 61-65 - 2007
- [c15]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD 2007: 212-219 - [c14]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC 2007: 187-190 - [c13]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design 2007: 308-313 - 2006
- [c12]Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP 2006: 113-120 - 2005
- [j3]Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen:
Modeling delay and noise in arbitrarily coupled RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1725-1739 (2005) - [c11]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS 2005: 277-285 - 2004
- [j2]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen:
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integr. 38(1): 3-17 (2004) - [c10]Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
Crosstalk immune interconnect driver design. SoC 2004: 139-142 - 2003
- [j1]Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 224-243 (2003) - [c9]Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen:
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. ICCAD 2003: 835-842 - [c8]Dinesh Pamunuwa, Shauki Elassaad:
Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. ISCAS (4) 2003: 604-607 - [c7]Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
A global wire planning scheme for Network-on-Chip. ISCAS (4) 2003: 892-895 - [c6]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch:
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362- - 2002
- [c5]Hannu Tenhunen, Dinesh Pamunuwa:
On dynamic delay and repeater insertion. ISCAS (1) 2002: 97-100 - [c4]Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) 2002: 193-196 - [c3]Dinesh Pamunuwa, Hannu Tenhunen:
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ISQED 2002: 240-245 - 2001
- [c2]Dinesh Pamunuwa, Hannu Tenhunen:
Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design 2001: 513-517 - 2000
- [c1]Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Combating digital noise in high speed ULSI circuits using binary BCH encoding. ISCAS 2000: 13-16
Coauthor Index
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