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ORCIDLuca Macchiarulo
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2010 – 2019
- 2011
[c29]Xin Gao, Luca Macchiarulo
:
A jumper insertion algorithm under antenna ratio and timing constraints. ICCAD 2011: 290-297- 2010
- [j11]Wansuree Massagram, Noah Hafner, Mingqi Chen, Luca Macchiarulo, Victor Lubecke, Olga Boric-Lubecke:
Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC. IEEE Trans. Biomed. Circuits Syst. 4(1): 19-26 (2010) - [c28]Xin Gao, Luca Macchiarulo:
Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. DATE 2010: 1279-1284
2000 – 2009
- 2009
- [j10]Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni:
A Case Study for NoC-Based Homogeneous MPSoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 384-388 (2009) - [c27]Mario R. Casu, Luca Macchiarulo:
Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. FMGALS@DATE 2009: 35-50 - 2007
- [j9]Mario R. Casu, Luca Macchiarulo:
Adaptive Latency-Insensitive Protocols. IEEE Des. Test Comput. 24(5): 442-452 (2007) - 2006
- [j8]Mario R. Casu, Luca Macchiarulo:
Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2996-3004 (2006) - [c26]Luca Macchiarulo:
Using Existing Digital Tools for Efficient Metabolic Pathway Simulations. EMBC 2006: 4233-4236 - [c25]Xiaoyue Wang, Mingqi Chen, Luca Macchiarulo, Olga Boric-Lubecke:
Fully-Integrated Heart Rate Variability Monitoring System with an Efficient Memory. EMBC 2006: 5064-5067 - [c24]Sergio Tota, Mario R. Casu, Luca Macchiarulo:
Implementation analysis of NoC: a MPSoC trace-driven approach. ACM Great Lakes Symposium on VLSI 2006: 204-209 - 2005
- [j7]Mario R. Casu, Luca Macchiarulo:
Throughput-driven floorplanning with wire pipelining. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 663-675 (2005) - [c23]Mario R. Casu, Luca Macchiarulo:
A New System Design Methodology for Wire Pipelined SoC. DATE 2005: 944-945 - [c22]Mario R. Casu, Luca Macchiarulo:
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ISPD 2005: 121-128 - 2004
- [j6]Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska:
Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53(9): 1205-1210 (2004) - [c21]Mario R. Casu, Luca Macchiarulo:
A new approach to latency insensitive design. DAC 2004: 576-581 - [c20]Mario R. Casu, Luca Macchiarulo:
Issues in Implementing Latency Insensitive Protocols. DATE 2004: 1390-1391 - [c19]Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini:
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ACM Great Lakes Symposium on VLSI 2004: 436-439 - [c18]Mario R. Casu, Luca Macchiarulo:
On-Chip Transparent Wire Pipelining. ICCD 2004: 160-167 - [c17]Mario R. Casu, Luca Macchiarulo:
Floorplanning for throughput. ISPD 2004: 62-69 - 2003
- [j5]Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
New techniques for efficiently assessing reliability of SOCs. Microelectron. J. 34(1): 53-61 (2003) - [j4]Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska:
PITIA: an FPGA for throughput-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 354-363 (2003) - 2002
- [j3]Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electron. Test. 18(3): 261-271 (2002) - [j2]Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino:
Layout-driven memory synthesis for embedded systems-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 96-105 (2002) - [c16]Luca Macchiarulo, Enrico Macii, Massimo Poncino:
Wire Placement for Crosstalk Energy Minimization in Address Buses. DATE 2002: 158-162 - [c15]Pierluigi Civera, Luca Macchiarulo, Massimo Violante:
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT 2002: 31-39 - [c14]Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino:
Enhanced clustered voltage scaling for low power. ACM Great Lakes Symposium on VLSI 2002: 18-23 - 2001
- [c13]Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304- - [c12]Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino:
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. DAC 2001: 784-789 - [c11]Luca Macchiarulo, Luca Benini, Enrico Macii:
On-the-fly layout generation for PTL macrocells. DATE 2001: 546-551 - [c10]Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258 - [c9]Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502 - [c8]Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13 - [c7]Luca Macchiarulo, Enrico Macii, Massimo Poncino:
Low-energy for deep-submicron address buses. ISLPED 2001: 176-181 - 2000
- [j1]Elena Dubrova, Luca Macchiarulo:
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. IEEE Trans. Computers 49(11): 1290-1292 (2000) - [c6]Luca Macchiarulo, Malgorzata Marek-Sadowska:
Wave-steering one-hot encoded FSMs. DAC 2000: 357-360 - [c5]Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska:
Wave Steered FSMs. DATE 2000: 270-276 - [c4]Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska:
A novel high throughput reconfigurable FPGA architecture. FPGA 2000: 22-29
1990 – 1999
- 1999
- [c3]Luca Macchiarulo, Pierluigi Civera:
Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. VLSI Design 1999: 218- - 1998
- [c2]Y. Bellan, Mario Costa, Giancarlo Ferrigno, Fabrizio Lombardi, Luca Macchiarulo, Alfonso Montuori, Eros Pasero, Camilla Rigotti:
Artificial Neural Networks for Motion Emulation in Virtual Environments. CAPTECH 1998: 83-99 - [c1]Luca Macchiarulo, Pierluigi Civera:
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. ISMVL 1998: 58-64
Coauthor Index
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