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"A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR ..."

Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund (2015)

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DOI: 10.1109/TVLSI.2014.2350540

access: closed

type: Journal Article

metadata version: 2020-03-11

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Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund:
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1941-1945 (2015)

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