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Siavash Bayat Sarmadi
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2020 – today
- 2024
- [j31]Farhad Taheri, Siavash Bayat Sarmadi, Hamed Rastaghi:
PartialHD: Toward Efficient Hyperdimensional Computing by Partial Processing. IEEE Internet Things J. 11(1): 987-994 (2024) - [j30]Hatameh Mosanaei-Boorani, Siavash Bayat Sarmadi:
A Digital Signature Architecture Suitable for V2V Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 731-739 (2024) - 2023
- [j29]Farhad Taheri Ardakani, Siavash Bayat Sarmadi:
MISC: Multi-Input Secure Two-Party Computation. ISC Int. J. Inf. Secur. 15(2) (2023) - [i5]Farhad Taheri, Siavash Bayat Sarmadi, Alireza Sadeghpour, Seyed Parsa Tayefeh Morsal:
Comprehensive Evaluation of RSB and Spectre Vulnerability on Modern Processors. CoRR abs/2302.09544 (2023) - [i4]Farhad Taheri, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Reza Taheri:
Fixflow: A Framework to Evaluate Fixed-point Arithmetic in Light-Weight CNN Inference. CoRR abs/2302.09564 (2023) - 2022
- [j28]Shahriar Hadayeghparast, Siavash Bayat Sarmadi, Shahriar Ebrahimi:
High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT. IEEE Internet Things J. 9(17): 15839-15846 (2022) - [j27]Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Hadayeghparast:
RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference. IEEE Internet Things J. 9(23): 24030-24037 (2022) - [j26]Mohammad Erfan Mazaheri, Siavash Bayat Sarmadi, Farhad Taheri Ardakani:
A Study of Timing Side-Channel Attacks and Countermeasures on JavaScript and WebAssembly. ISC Int. J. Inf. Secur. 14(1): 27-46 (2022) - [j25]Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Armin Alivand:
Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1221-1230 (2022) - [j24]Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Ebrahimi:
Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1231-1239 (2022) - 2021
- [j23]Mohsen Salehi, Siavash Bayat Sarmadi:
PLCDefender: Improving Remote Attestation Techniques for PLCs Using Physical Model. IEEE Internet Things J. 8(9): 7372-7379 (2021) - [j22]Shahriar Ebrahimi, Siavash Bayat Sarmadi:
Lightweight Fuzzy Extractor Based on LPN for Device and Biometric Authentication in IoT. IEEE Internet Things J. 8(13): 10706-10713 (2021) - [j21]Nastaran Shekofte, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani:
A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration. ISC Int. J. Inf. Secur. 13(1): 29-45 (2021) - [j20]Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Armin Alivand:
Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2042-2050 (2021) - 2020
- [j19]Shahriar Ebrahimi, Siavash Bayat Sarmadi:
Lightweight and Fault-Resilient Implementations of Binary Ring-LWE for IoT Devices. IEEE Internet Things J. 7(8): 6970-6978 (2020) - [j18]Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani:
Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key Encapsulation Using an Efficient Scheduling. IEEE Trans. Circuits Syst. 67-I(12): 4895-4903 (2020) - [c11]Mohammad Erfan Mazaheri, Farhad Taheri, Siavash Bayat Sarmadi:
Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly. ISCISC 2020: 1-6
2010 – 2019
- 2019
- [j17]Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi:
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. J. Electron. Test. 35(2): 201-214 (2019) - [j16]Shahriar Ebrahimi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani:
Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT. IEEE Internet Things J. 6(3): 5500-5507 (2019) - [j15]Mohammad Sadegh Sadeghi, Siavash Bayat Sarmadi, Shaahin Hessabi:
Toward On-chip Network Security Using Runtime Isolation Mapping. ACM Trans. Archit. Code Optim. 16(3): 28:1-28:25 (2019) - [j14]Taha Shahroodi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani:
Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1465-1473 (2019) - [j13]Raziyeh Salarifard, Siavash Bayat Sarmadi:
An Efficient Low-Latency Point-Multiplication Over Curve25519. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3854-3862 (2019) - [c10]Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, A.-Bon E. Ackie, Reza Azarderakhsh:
High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE. LASCAS 2019: 201-204 - 2018
- [j12]Raziyeh Salarifard, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani:
A Low-Latency and Low-Complexity Point-Multiplication in ECC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2869-2877 (2018) - [c9]Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi:
Reliable hardware architectures for efficient secure hash functions ECHO and fugue. CF 2018: 204-207 - [i3]Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi:
Lightweight Hardware Architectures for Efficient Secure Hash Functions ECHO and Fugue. CoRR abs/1804.06497 (2018) - 2017
- [c8]Mohammad Hossein Yalame, Mohammad Hossein Farzam, Siavash Bayat Sarmadi:
Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer. ATIS 2017: 23-34 - 2016
- [j11]Raziyeh Salarifard, Siavash Bayat Sarmadi, Mohammad Farmani:
High-Throughput Low-Complexity Unified Multipliers Over GF(2m) in Dual and Triangular Bases. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1944-1953 (2016) - [i2]Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili:
Efficient Lattice-based Authenticated Encryption: A Practice-Oriented Provable Security Approach. IACR Cryptol. ePrint Arch. 2016: 268 (2016) - 2015
- [j10]Behnam Khaleghi, Ali Ahari, Hossein Asadi, Siavash Bayat Sarmadi:
FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. IEEE Embed. Syst. Lett. 7(2): 46-50 (2015) - [j9]Siavash Bayat Sarmadi, Mohammad Farmani:
High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2m) Based on Trinomials. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 377-381 (2015) - [j8]Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili:
On Constrained Implementation of Lattice-Based Cryptographic Primitives and Schemes on Smart Cards. ACM Trans. Embed. Comput. Syst. 14(3): 42:1-42:25 (2015) - [j7]Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, Chiou-Yng Lee:
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1969-1972 (2015) - 2014
- [j6]Mehran Mozaffari Kermani, Kai Tian, Reza Azarderakhsh, Siavash Bayat Sarmadi:
Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems. IEEE Embed. Syst. Lett. 6(4): 89-92 (2014) - [j5]Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Arash Reyhani-Masoleh:
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1105-1109 (2014) - [j4]Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee:
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. IEEE Trans. Circuits Syst. II Express Briefs 61-II(2): 125-129 (2014) - [j3]Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi:
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 22(5): 995-1003 (2014) - [c7]Ahmad Boorghany, Siavash Bayat Sarmadi, Pamian Yousefi, Pouneh Gorji, Rasool Jalili:
Random data and key generation evaluation of some commercial tokens and smart cards. ISCISC 2014: 49-54 - [i1]Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili:
On Constrained Implementation of Lattice-based Cryptographic Primitives and Schemes on Smart Cards. IACR Cryptol. ePrint Arch. 2014: 514 (2014)
2000 – 2009
- 2009
- [j2]Siavash Bayat Sarmadi, M. Anwar Hasan:
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures. IEEE Trans. Computers 58(11): 1553-1567 (2009) - 2007
- [j1]Siavash Bayat Sarmadi, M. Anwar Hasan:
On Concurrent Detection of Errors in Polynomial Basis Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 413-426 (2007) - [c6]Siavash Bayat Sarmadi, M. Anwar Hasan:
Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes. ASAP 2007: 204-209 - [c5]Siavash Bayat Sarmadi, M. Anwar Hasan:
Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs. ICCD 2007: 368-375 - 2005
- [c4]Siavash Bayat Sarmadi, M. Anwar Hasan:
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. DFT 2005: 102-110 - 2003
- [c3]Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi:
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN 2003: 479-488 - 2002
- [c2]Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali:
Fast Prototyping with Co-operation of Simulation and Emulation. FPL 2002: 15-25 - [c1]Seyed Ghassem Miremadi, Siavash Bayat Sarmadi, Ghazanfar Asadi:
Speedup analysis in simulation-emulation co-operation. FPT 2002: 394-398
Coauthor Index
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last updated on 2024-10-07 22:18 CEST by the dblp team
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