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Wen-Ben Jone
Person information
- affiliation: University of Cincinnati, USA
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2010 – 2019
- 2018
- [j55]Qiang Han, Qiang Xu
, Wen-Ben Jone:
SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits. Integr. 60: 1-12 (2018) - 2017
- [j54]Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. ACM Trans. Design Autom. Electr. Syst. 22(3): 46:1-46:27 (2017) - 2016
- [j53]Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1169-1173 (2016) - 2015
- [j52]Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1628-1639 (2015) - [c63]Qiang Han, Jianghao Guo, Qiang Xu
, Wen-Ben Jone:
On Resilient System Performance Binning. ISPD 2015: 119-125 - 2014
- [c62]Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu:
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. ACM Great Lakes Symposium on VLSI 2014: 233-234 - 2013
- [j51]Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone:
Testing of Synchronizers in Asynchronous FIFO. J. Electron. Test. 29(1): 49-72 (2013) - [c61]Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu
:
On testing timing-speculative circuits. DAC 2013: 30:1-30:6 - [c60]Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu
:
Post-placement voltage island generation for timing-speculative circuits. DAC 2013: 112:1-112:6 - [c59]Jianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu:
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability. DFTS 2013: 71-76 - [c58]Qiang Han, Jianghao Guo, Wen-Ben Jone, Qiang Xu
:
Path delay testing in resilient system. MWSCAS 2013: 645-648 - [c57]Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen:
A configurable bus-tracer for error reproduction in post-silicon validation. VLSI-DAT 2013: 1-4 - 2012
- [j50]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang:
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17(4): 48:1-48:16 (2012) - [c56]Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen:
IMITATOR: A deterministic multicore replay system with refining techniques. VLSI-DAT 2012: 1-4 - 2011
- [j49]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu:
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 455-463 (2011) - [j48]Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu:
Location Cache Design and Performance Analysis for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 104-117 (2011) - [j47]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Dynamic Characteristics of Power Gating During Mode Transition. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 237-249 (2011) - [j46]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth Hopping With Temperature and Process Variation. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1319-1323 (2011) - 2010
- [j45]Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang:
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. J. Electron. Test. 26(3): 367-392 (2010) - [j44]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Tuning Vth Hopping for Aggressive Runtime Leakage Control. J. Low Power Electron. 6(3): 447-456 (2010) - [j43]Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone:
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 299-312 (2010) - [c55]Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang:
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT 2010: 358-366 - [c54]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD 2010: 632-636 - [c53]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD 2010: 637-641 - [c52]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design 2010: 51-56
2000 – 2009
- 2009
- [j42]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. 26(1): 26-35 (2009) - [c51]Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu:
Analysis of Resistive Bridging Defects in a Synchronizer. Asian Test Symposium 2009: 443-449 - [c50]Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. DATE 2009: 594-597 - [c49]Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang:
Analysis of Resistive Open Defects in a Synchronizer. DFT 2009: 164-172 - [c48]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Temporal and spatial idleness exploitation for optimal-grained leakage control. ICCAD 2009: 468-473 - 2008
- [j41]Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf
, Wen-Ben Jone, Mehmet Sahinoglu:
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. IEEE Trans. Instrum. Meas. 57(10): 2146-2168 (2008) - [c47]Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Control Circuitry for Self-Repairable MEMS Accelerometers. EIAT/IETA 2008: 265-270 - [c46]Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Material Fatigue and Reliability of MEMS Accelerometers. DFT 2008: 314-322 - [c45]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Accurate energy breakeven time estimation for run-time power gating. ICCAD 2008: 161-168 - [c44]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. ICCD 2008: 618-625 - [c43]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Dynamic virtual ground voltage estimation for power gating. ISLPED 2008: 27-32 - [c42]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9 - 2007
- [j40]Wei Pei, Wen-Ben Jone, Yiming Hu:
Fault Modeling and Detection for Drowsy SRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1084-1100 (2007) - [j39]Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf
, Amiya Nayak
, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu:
Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. IEEE Trans. Instrum. Meas. 56(3): 840-855 (2007) - [c41]Jianxun Liu, Wen-Ben Jone:
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. ICCD 2007: 360-367 - 2006
- [j38]Jianxun Liu, Wen-Ben Jone, Sunil R. Das:
Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE Trans. Instrum. Meas. 55(4): 1288-1302 (2006) - [c40]Ming Li, Qing-An Zeng, Wen-Ben Jone:
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. DAC 2006: 849-852 - [c39]Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Reliability Analysis of Self-Repairable MEMS Accelerometer. DFT 2006: 236-244 - [c38]Ming Li, Wen-Ben Jone, Qing-An Zeng:
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. ISVLSI 2006: 147-152 - [c37]Wei Pei, Wen-Ben Jone, Yiming Hu:
Fault Modeling and Detection for Drowsy SRAM Caches. ITC 2006: 1-10 - 2005
- [j37]Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf
, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu:
Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. IEEE Trans. Instrum. Meas. 54(5): 1662-1677 (2005) - [j36]Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das:
A built-in self-testing method for embedded multiport memory arrays. IEEE Trans. Instrum. Meas. 54(5): 1721-1738 (2005) - [j35]Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
A dual-mode built-in self-test technique for capacitive MEMS devices. IEEE Trans. Instrum. Meas. 54(5): 1739-1750 (2005) - [j34]Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf
, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu:
Fault simulation and response compaction in full scan circuits using HOPE. IEEE Trans. Instrum. Meas. 54(6): 2310-2328 (2005) - [c36]Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone:
Design and design automation of rectification logic for engineering change. ASP-DAC 2005: 1006-1009 - [c35]Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Design and Analysis of Self-Repairable MEMS Accelerometer. DFT 2005: 21-32 - 2004
- [j33]Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das:
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 53(4): 915-932 (2004) - [c34]Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang:
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. Asian Test Symposium 2004: 210-215 - [c33]Rui Min, Wen-Ben Jone, Yiming Hu:
Phased tag cache: an efficient low power cache system. ISCAS (2) 2004: 805-808 - [c32]Rui Min, Wen-Ben Jone, Yiming Hu:
Location cache: a low-power L2 cache system. ISLPED 2004: 120-125 - [c31]Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone:
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. VLSI Design 2004: 183-188 - [c30]Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. VTS 2004: 148-153 - 2003
- [j32]Sunil R. Das, Made Sudarma
, Mansour H. Assaf
, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty
, Mehmet Sahinoglu:
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. IEEE Trans. Instrum. Meas. 52(5): 1363-1380 (2003) - [j31]Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das:
An efficient BIST method for non-traditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 52(5): 1381-1390 (2003) - [j30]Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen:
Design theory and implementation for low-power segmented bus systems. ACM Trans. Design Autom. Electr. Syst. 8(1): 38-54 (2003) - [j29]J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh:
Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Trans. Reliab. 52(4): 435-443 (2003) - 2002
- [j28]Der-Cheng Huang, Wen-Ben Jone:
A parallel built-in self-diagnostic method for embedded memoryarrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 449-465 (2002) - [j27]Der-Cheng Huang, Wen-Ben Jone:
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 617-628 (2002) - [j26]Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf
, Wen-Ben Jone, Krishnendu Chakrabarty
:
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. IEEE Trans. Instrum. Meas. 51(1): 150-172 (2002) - [j25]Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee:
An efficient BIST method for distributed small buffers. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 512-515 (2002) - 2001
- [j24]Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 266-280 (2001) - [j23]Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das:
An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. 50(5): 1109-1118 (2001) - [j22]Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf
, Emil M. Petriu, Wen-Ben Jone:
Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. IEEE Trans. Instrum. Meas. 50(6): 1725-1747 (2001) - [j21]Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das:
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. VLSI Design 12(4): 457-474 (2001) - [j20]Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das:
Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design 12(4): 537-549 (2001) - [c29]J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone:
Embedded Core Testing Using Broadcast Test Architecture. DFT 2001: 95-103 - [c28]Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design 2001: 379-384 - [c27]Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design 2001: 397-402 - 2000
- [j19]Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang:
TAIR: testability analysis by implication reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 152-160 (2000) - [c26]Der-Cheng Huang, Wen-Ben Jone:
An efficient parallel transparent diagnostic BIST. Asian Test Symposium 2000: 299- - [c25]Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440 - [c24]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337 - [c23]Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390 - [c22]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW 2000: 59-64
1990 – 1999
- 1999
- [j18]J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen:
Segmented bus design for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 25-29 (1999) - [c21]Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC 1999: 68-71 - [c20]Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85 - [c19]Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) 1999: 246-249 - [c18]Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee:
An Efficient BIST Method for Small Buffers. VTS 1999: 246-251 - 1998
- [j17]Wen-Ben Jone, K. S. Tsai:
Confidence analysis for defect-level estimation of VLSI random testing. ACM Trans. Design Autom. Electr. Syst. 3(3): 389-407 (1998) - [j16]Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak
:
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. VLSI Design 7(2): 191-201 (1998) - [c17]Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330 - [c16]Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai:
A novel combinational testability analysis by considering signal correlation. ITC 1998: 658-667 - [c15]Wen-Ben Jone, Sunil R. Das:
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. VLSI Design 1998: 382- - 1997
- [j15]Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Variable Observation Times. J. Electron. Test. 11(2): 131-146 (1997) - [c14]Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Multiple Test Observation Times. VLSI Design 1997: 106-110 - 1996
- [j14]Dan Li, Wen-Ben Jone:
Pseudorandom test-length analysis using differential solutions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 815-825 (1996) - [j13]Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das:
PGEN: A Novel Approach to Sequential Circuit Test Generation. VLSI Design 4(3): 149-165 (1996) - [c13]Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak:
Syndrome signature in output compaction for VLSI BIST. VLSI Design 1996: 337-338 - 1995
- [j12]Chen-Liang Fang, Wen-Ben Jone:
Timing optimization by gate resizing and critical path identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 201-217 (1995) - [j11]Wen-Ben Jone, Christos A. Papachristou:
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 374-384 (1995) - [j10]Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak
, Ian Choi:
On testing of sequential machines using circuit decomposition and stochastic modeling. IEEE Trans. Syst. Man Cybern. 25(3): 489-504 (1995) - [j9]Wen-Ben Jone, Sunil R. Das:
CACOP-a random pattern testability analyzer. IEEE Trans. Syst. Man Cybern. 25(5): 865-871 (1995) - [j8]Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr:
Realizing a high measure of confidence for defect level analysis of random testing [VLSI]. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 446-450 (1995) - [c12]Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak:
An improved output compaction technique for built-in self-test in VLSI circuits. VLSI Design 1995: 403-407 - 1994
- [j7]Wen-Ben Jone, Cheng-Juei Wu:
Multiple Fault Detection in Parity Checkers. IEEE Trans. Computers 43(9): 1096-1099 (1994) - [c11]Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das:
Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. ICPADS 1994: 360-365 - [c10]Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi:
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. VLSI Design 1994: 311-314 - 1993
- [j6]Wen-Ben Jone, Patrick H. Madden:
Multiple fault testing using minimal single fault test set for fanout-free circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 149-157 (1993) - [j5]Wen-Ben Jone:
Defect level estimation of circuit testing using sequential statistical analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 336-348 (1993) - [c9]Wen-Ben Jone, Chen-Liang Fang:
Timing Optimization By Gate Resizing And Critical Path Identification. DAC 1993: 135-140 - [c8]Cheng-Juei Wu, Wen-Ben Jone:
On Multiple Fault Detection of Parity Checkers. ISCAS 1993: 1515-1518 - [c7]Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone:
Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing. ITC 1993: 478-487 - [c6]Wen-Ben Jone, Sunil R. Das:
CACOP - A Random Pattern Testability Analyzer. VLSI Design 1993: 61-64 - 1992
- [j4]Sunil R. Das, Wen-Ben Jone:
On random testing for combinational circuits with a high measure of confidence. IEEE Trans. Syst. Man Cybern. 22(4): 748-754 (1992) - 1991
- [j3]Wen-Ben Jone, Anita Gleason:
Analysis of Hamming count compaction scheme. J. Electron. Test. 2(4): 373-384 (1991) - [c5]Anita Gleason, Wen-Ben Jone:
Reduced Hamming Count and Its Aliasing Probability. ICCD 1991: 356-359 - [c4]Wen-Ben Jone:
Defect Level Estimation of Random and Pseudorandom Testing. ITC 1991: 712-721 - 1990
- [j2]Wen-Ben Jone, Sunil R. Das:
Multiple-output parity bit signature for exhaustive testing. J. Electron. Test. 1(2): 175-178 (1990) - [j1]Sunil R. Das, Wen-Ben Jone, K. L. Wong:
Probabilistic modeling and fault analysis in sequential logic using computer simulation. IEEE Trans. Syst. Man Cybern. 20(2): 490-498 (1990)
1980 – 1989
- 1989
- [c3]Wen-Ben Jone, Christos A. Papachristou:
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. DAC 1989: 525-534 - [c2]Wen-Ben Jone, Christos A. Papachristou, M. Pereira:
A Scheme for Overlaying Concurrent Testing of VLSI Circuits. DAC 1989: 531-536 - [c1]Anita Gleason, Wen-Ben Jone:
Hamming count-a compaction testing technique. ICCD 1989: 344-347
Coauthor Index
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
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OpenAlex data
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last updated on 2024-04-24 22:58 CEST by the dblp team
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