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2020 – today
- 2024
[j16]Chaitanya Bhure, Geraldine Shirley Nicholas, Shajib Ghosh, Navid Asadi, Fareena Saqib:
AutoDetect: Novel Autoencoding Architecture for Counterfeit IC Detection. J. Hardw. Syst. Secur. 8(2): 113-132 (2024)- 2023
- [j15]Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib:
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V. Cryptogr. 7(4): 58 (2023) - [i1]Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib:
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V. CoRR abs/2311.10283 (2023) - 2022
- [c22]Jakub Slowik, Gregory Williams, Rummah Albashir, Anthony Samagio, Geraldine Shirley Nicholas, Fareena Saqib:
Dynamic Key Updates for LUT Locked Design. HOST 2022: 105-108 - 2021
- [j14]Yutian Gui, Chaitanya Bhure
, Marcus Hughes, Fareena Saqib:
A Delay-Based Machine Learning Model for DMA Attack Mitigation. Cryptogr. 5(3): 18 (2021) - [j13]Geraldine Shirley Nicholas, Ali Shuja Siddiqui, Sam Reji Joseph, Gregory Williams, Fareena Saqib:
A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic. J. Hardw. Syst. Secur. 5(3): 260-268 (2021) - [c21]Geraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib:
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V. ACM Great Lakes Symposium on VLSI 2021: 409-414 - [c20]Yutian Gui, Ali Shuja Siddiqui, Geraldine Shirley Nicholas, Marcus Hughes, Fareena Saqib:
A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation. ISQED 2021: 263-268 - [c19]Gregory Williams, Jerry Aizprua, Mohammad Alhaddad, Doua Yang, Nabila BouSaba, Fareena Saqib:
A SoC Design of TrustZone based Key Provisioning for FPGA IP Protection. MWSCAS 2021: 874-877 - 2020
- [j12]Ivan Bow, Nahome Bete, Fareena Saqib, Wenjie Che, Chintan Patel, Ryan W. Robucci, Calvin Chan, Jim Plusquellic:
Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity. Cryptogr. 4(2): 13 (2020) - [j11]Ali Shuja Siddiqui, Yutian Gui, Fareena Saqib:
Secure Boot for Reconfigurable Architectures. Cryptogr. 4(4): 26 (2020) - [j10]Yutian Gui, Suyash Mohan Tamore, Ali Shuja Siddiqui, Fareena Saqib:
Key Update Countermeasure for Correlation-Based Side-Channel Attacks. J. Hardw. Syst. Secur. 4(3): 167-179 (2020) - [c18]Geraldine Shirley Nicholas, Yutian Gui, Fareena Saqib:
A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture. MWSCAS 2020: 718-721
2010 – 2019
- 2019
- [j9]Jeff Calhoun, Cyrus Minwalla, Charles Helmich, Fareena Saqib, Wenjie Che, Jim Plusquellic:
Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash). Cryptogr. 3(3): 18 (2019) - [c17]Yutian Gui, Ali Shuja Siddiqui, Suyash Mohan Tamore, Fareena Saqib:
Security Vulnerabilities of Smart Meters in Smart Grid. IECON 2019: 3018-3023 - [c16]Bryson Shannon, Spandana Etikala, Yutian Gui, Ali Shuja Siddiqui, Fareena Saqib:
Blockchain Based Distributed Key Provisioning and Secure Communication over CAN FD. ISVLSI 2019: 638-644 - [c15]Ali Shuja Siddiqui, Geraldine Shirley, Shreya Bendre, Girija Bhagwat, Jim Plusquellic, Fareena Saqib:
Secure Design Flow of FPGA Based RISC-V Implementation. IVSW 2019: 37-42 - [c14]Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib:
Multilayer Camouflaged Secure Boot for SoCs. MTV 2019: 56-61 - 2018
- [j8]Don Owen Jr., Derek Heeger, Calvin Chan, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic:
An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays. Cryptogr. 2(3): 15 (2018) - [j7]Wenjie Che, Fareena Saqib, Jim Plusquellic:
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 733-743 (2018) - [c13]Wenjie Che, Manel Martínez-Ramón, Fareena Saqib, Jim Plusquellic:
Delay model and machine learning exploration of a hardware-embedded delay PUF. HOST 2018: 153-158 - [c12]Goutham Pocklassery, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic:
Self-authenticating secure boot for FPGAs. HOST 2018: 221-226 - [c11]Ali Shuja Siddiqui, Yutian Gui, David Lawrence, Stuart Laval, Jim Plusquellic, Madhav D. Manjrekar, Badrul H. Chowdhury, Fareena Saqib:
Hardware Assisted Security Architecture for Smart Grid. IECON 2018: 2890-2895 - 2017
- [j6]Wenjie Che, Mitchell T. Martin, Goutham Pocklassery, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic:
A Privacy-Preserving, Mutual PUF-Based Authentication Protocol. Cryptogr. 1(1): 3 (2017) - [j5]Wenjie Che, Venkata K. Kajuluri, Mitchell T. Martin, Fareena Saqib, Jim Plusquellic:
Analysis of Entropy in a Hardware-Embedded Delay PUF. Cryptogr. 1(1): 8 (2017) - [j4]Wenjie Che, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic:
Leveraging Distributions in Physical Unclonable Functions. Cryptogr. 1(3): 17 (2017) - [c10]Ali Shuja Siddiqui, Chia-Che Lee, Wenjie Che, Jim Plusquellic, Fareena Saqib:
Secure intra-vehicular communication over CANFD. AsianHOST 2017: 97-102 - [c9]Goutham Pocklassery, Venkata K. Kajuruli, James F. Plusquellic, Fareena Saqib:
Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems. HOST 2017: 116-121 - [c8]Wenjie Che, Jim Plusquellic, Fareena Saqib:
A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF. HOST 2017: 157 - [c7]Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib:
Secure communication over CANBus. MWSCAS 2017: 1264-1267 - [c6]Ali Shuja Siddiqui, Chia-Che Lee, Fareena Saqib:
Hardware based protection against malwares by PUF based access control mechanism. MWSCAS 2017: 1312-1315 - 2016
- [c5]Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib:
On detecting delay anomalies introduced by hardware trojans. ICCAD 2016: 44 - [c4]Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib:
Poster: Hardware based security enhanced framework for automotives. VNC 2016: 1-2 - 2015
- [j3]Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios S. Pattichis:
Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF). IEEE Trans. Computers 64(1): 280-285 (2015) - [j2]Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic:
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 776-780 (2015) - [c3]Charalambos Konstantinou, Michail Maniatakos, Fareena Saqib, Shiyan Hu, Jim Plusquellic, Yier Jin:
Cyber-physical systems: A security perspective. ETS 2015: 1-8 - [c2]I. Wilcox, Fareena Saqib, James F. Plusquellic:
GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units. HOST 2015: 144-150 - [c1]Wenjie Che, Fareena Saqib, Jim Plusquellic:
PUF-Based Authentication. ICCAD 2015: 337-344 - 2014
- [j1]Fareena Saqib, Matthew Areno, Jim Aarestad, James F. Plusquellic:
ASIC implementation of a hardware-embedded physical unclonable function. IET Comput. Digit. Tech. 8(6): 288-299 (2014)
Coauthor Index
aka: Jim Plusquellic
aka: Geraldine Shirley Nicholas
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last updated on 2024-10-02 21:40 CEST by the dblp team
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