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2010 – 2019
- 2017
[j3]Cody Miller, Dae Glendowne, Henry Cook, Thomas DeMarcus, Chris Lanclos, Patrick Pape:
Insights gained from constructing a large scale dynamic analysis platform. Digit. Investig. 22 Supplement: S48-S56 (2017)- [c12]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avizienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Microprocessor chip with photonic I/O. OFC 2017: 1-3 - 2016
- [b1]Henry Cook:
Productive Design of Extensible On-Chip Memory Hierarchies. University of California, Berkeley, USA, 2016 - [j2]Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic:
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36(2): 8-20 (2016) - 2015
- [j1]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael Georgas, Andrew Waterman, Jeffrey M. Shainline, Rimas Avizienis, Sen Lin, Benjamin Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Single-chip microprocessor that communicates directly using light. Nat. 528(7581): 534-538 (2015) - [c11]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic:
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - 2014
- [c10]Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic:
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. ESSCIRC 2014: 199-202 - 2013
- [c9]Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic:
The RISC-V instruction set. Hot Chips Symposium 2013: 1 - [c8]Henry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David A. Patterson, Krste Asanovic:
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. ISCA 2013: 308-319 - 2012
- [c7]Shoaib Kamil, Derrick Coetzee, Scott Beamer, Henry Cook, Ekaterina Gonina, Jonathan Harper, Jeffrey Morlan, Armando Fox:
Portable parallel performance from sequential, productive, embedded domain-specific languages. PPoPP 2012: 303-304 - 2011
- [c6]Ekaterina Gonina, Gerald Friedland, Henry Cook, Kurt Keutzer:
Fast speaker diarization using a high-level scripting language. ASRU 2011: 553-558 - [c5]Henry Cook, Ekaterina Gonina, Shoaib Kamil, Gerald Friedland, David A. Patterson, Armando Fox:
CUDA-level Performance with Python-level Productivity for Gaussian Mixture Model Applications. HotPar 2011 - [c4]Michael Bauer, Henry Cook, Brucek Khailany:
CudaDMA: optimizing GPU memory bandwidth via warp specialization. SC 2011: 12:1-12:11 - 2010
- [c3]Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic:
RAMP gold: an FPGA-based architecture simulator for multiprocessors. DAC 2010: 463-468 - [c2]Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson:
A case for FAME: FPGA architecture model execution. ISCA 2010: 290-301
2000 – 2009
- 2008
- [c1]Henry Cook, Kevin Skadron:
Predictive design space exploration using genetically programmed response surfaces. DAC 2008: 960-965
Coauthor Index
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