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Peter M. Kogge
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- award: 2015 Computer Pioneer Award
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2020 – today
- 2024
- [c88]Jay Vap, Peter M. Kogge:
RIMR: Reverse Influence Maximization Rank. IPDPS (Workshops) 2024: 805-814 - 2023
- [c87]Peter M. Kogge:
HCW 2023 Keynote Heterogeneity and the Problem that Shall Not Be Named. IPDPS Workshops 2023: 5 - 2022
- [c86]Peter M. Kogge, William J. Dally:
Frontier vs the Exascale Report: Why so long? and Are We Really There Yet? PMBS@SC 2022: 26-35 - [c85]Brian A. Page
, Peter M. Kogge:
The Evolution of a New Model of Computation. IA3@SC 2022: 9-18 - [i1]Ruiyang Qin, Zhiding Liang, Jinglei Cheng, Peter M. Kogge, Yiyu Shi:
Improving Quantum Classifier Performance in NISQ Computers by Voting Strategy from Ensemble Learning. CoRR abs/2210.01656 (2022) - 2021
- [c84]Peter M. Kogge, Brian A. Page:
Locality: The 3rd Wall and the Need for Innovation in Parallel Architectures. ARCS 2021: 3-18 - [c83]Neil Butcher, Peter M. Kogge:
Exploring Strategies to Improve Locality Across Many-Core Affinities. Euro-Par Workshops 2021: 29-40 - [c82]Brian A. Page, Peter M. Kogge:
Deluge: Achieving Superior Efficiency, Throughput, and Scalability with Actor Based Streaming on Migrating Threads. HPEC 2021: 1-6 - [c81]Brian A. Page, Peter M. Kogge:
Greatly Accelerated Scaling of Streaming Problems with A Migrating Thread Architecture. IA3@SC 2021: 11-18 - [c80]Brian A. Page, Peter M. Kogge:
Passel: Improved Scalability and Efficiency of Distributed SVM using a Cacheless PGAS Migrating Thread Architecture. ScalA@SC 2021: 27-34 - [c79]Brian A. Page
, Peter M. Kogge
:
Scalability of Streaming Anomaly Detection in an Unbounded Key Space Using Migrating Threads. ISC 2021: 157-175 - 2020
- [c78]Steven J. Krieg, Peter M. Kogge, Nitesh V. Chawla
:
GrowHON: A Scalable Algorithm for Growing Higher-order Networks of Sequences. COMPLEX NETWORKS (2) 2020: 485-496 - [c77]Géraud Krawezik, Shannon K. Kuntz, Peter M. Kogge:
Implementing Sparse Linear Algebra Kernels on the Lucata Pathfinder-A Computer. HPEC 2020: 1-6 - [c76]Brian A. Page, Peter M. Kogge:
Scalability of Streaming on Migrating Threads. HPEC 2020: 1-8 - [c75]Paul L. Springer, Thomas Schibler, Géraud Krawezik, Jack Lightholder, Peter M. Kogge:
Machine Learning Algorithm Performance on the Lucata Computer. HPEC 2020: 1-7 - [c74]Brian A. Page, Peter M. Kogge:
Scalability of Sparse Matrix Dense Vector Multiply (SpMV) on a Migrating Thread Architecture. IPDPS Workshops 2020: 483-488 - [c73]Neil A. Butcher, Stephen L. Olivier
, Peter M. Kogge:
Cache Oblivious Strategies to Exploit Multi-Level Memory on Manycore Systems. MCHPC@SC 2020: 42-51
2010 – 2019
- 2019
- [c72]Peter M. Kogge:
Multi-threading Semantics for Highly Heterogeneous Systems Using Mobile Threads. HPCS 2019: 281-289 - [c71]Brian A. Page, Peter M. Kogge:
Scalability of Hybrid SpMV on Intel Xeon Phi Knights Landing. HPCS 2019: 348-357 - [c70]Peter M. Kogge, Neil A. Butcher, Brian A. Page:
Introducing Streaming into Linear Algebra-based Sparse Graph Algorithms. HPCS 2019: 486-495 - [c69]Vladimir Getov, Peter M. Kogge, Thomas M. Conte:
Application Performance of Physical System Simulations. PARCO 2019: 251-260 - 2018
- [c68]Géraud Krawezik, Peter M. Kogge, Timothy J. Dysart, Shannon K. Kuntz, Janice O. McMahon:
Implementing the Jaccard Index on the Migratory Memory-Side Processing Emu Architecture. HPEC 2018: 1-6 - [c67]Neil Butcher, Stephen L. Olivier
, Jonathan W. Berry, Simon D. Hammond, Peter M. Kogge:
Optimizing for KNL Usage Modes When Data Doesn't Fit in MCDRAM. ICPP 2018: 37:1-37:10 - [c66]Brian A. Page, Peter M. Kogge:
Scalability of Hybrid Sparse Matrix Dense Vector (SpMV) Multiplication. HPCS 2018: 406-414 - 2017
- [c65]Peter M. Kogge:
Graph Analytics: Complexity, Scalability, and Architectures. IPDPS Workshops 2017: 1039-1047 - [c64]Peter M. Kogge, Shannon K. Kuntz:
A Case for Migrating Execution for Irregular Applications. IA3@SC 2017: 6:1-6:8 - 2016
- [c63]Craig S. Lent, Kenneth W. Henderson, S. Alex Kandel, Steven A. Corcelli, Gregory L. Snider
, Alexei O. Orlov
, Peter M. Kogge, Michael T. Niemier, Ryan C. Brown, John A. Christie, Natalie A. Wasio, Rebecca C. Quardokus, Ryan P. Forrest, Jacob P. Peterson, Angela Silski, David A. Turner, Enrique P. Blair, Yuhui Lu:
Molecular cellular networks: A non von Neumann architecture for molecular electronics. ICRC 2016: 1-7 - [c62]Peter M. Kogge:
Jaccard Coefficients as a Potential Graph Benchmark. IPDPS Workshops 2016: 921-928 - [c61]Peter M. Kogge:
ParLearning 2016 Keynote. IPDPS Workshops 2016: 1392 - [c60]Timothy J. Dysart, Peter M. Kogge, Martin M. Deneroff, Eric Bovell, Preston Briggs, Jay B. Brockman, Kenneth Jacobsen, Yujen Juan, Shannon K. Kuntz, Richard A. Lethin, Janice O. McMahon, Chandra Pawar, Martin Perrigo, Sarah Rucker, John Ruttenberg, Max Ruttenberg, Steve Stein:
Highly Scalable Near Memory Processing with Migrating Threads on the Emu System Architecture. IA3@SC 2016: 2-9 - 2015
- [c59]Peter M. Kogge:
Updating the Energy Model for Future Exascale Systems. ISC 2015: 323-339 - 2014
- [c58]Peter M. Kogge:
Reading the Tea-Leaves: How Architecture Has Evolved at the High End. IPDPS 2014: 515 - 2013
- [j20]Peter M. Kogge, John Shalf
:
Exascale Computing Trends: Adjusting to the "New Normal"' for Computer Architecture. Comput. Sci. Eng. 15(6): 16-26 (2013) - [j19]Patrick Anthony La Fratta, Peter M. Kogge:
Energy-efficient multithreading for a hierarchical heterogeneous multicore through locality-cognizant thread generation. J. Parallel Distributed Comput. 73(12): 1551-1562 (2013) - [c57]Peter M. Kogge, David A. Bayliss:
Comparative performance analysis of a Big Data NORA problem on a variety of architectures. CTS 2013: 22-34 - [c56]Peter M. Kogge:
Big data, deep data, and the effect of system architectures on performance. CTS 2013: 40-41 - 2011
- [j18]Sheng Li, Shannon K. Kuntz, Jay B. Brockman, Peter M. Kogge:
Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip. IEEE Trans. Parallel Distributed Syst. 22(7): 1178-1191 (2011) - [c55]Megan Cason, Peter M. Kogge:
Recomposing an Irregular Algorithm Using a Novel Low-Level PGAS Model. ICPP Workshops 2011: 238-248 - [c54]Peter M. Kogge, Timothy J. Dysart:
Using the TOP500 to trace and project technology and architecture trends. SC 2011: 28:1-28:11 - 2010
- [c53]Patrick Anthony La Fratta, Peter M. Kogge:
Models for generating locality-tuned traveling threads for a hierarchical multi-level heterogeneous multicore. Conf. Computing Frontiers 2010: 227-236 - [c52]Patrick Anthony La Fratta, Peter M. Kogge:
Modeling bounds on migration overhead for a traveling thread architecture. IPDPS Workshops 2010: 1-8 - [c51]Peter M. Kogge:
Exploring the Possible Past Futures of a Single Part Type Multi-core PIM Chip. IWIA 2010: 30-38 - [c50]Peter M. Kogge, Patrick Anthony La Fratta, Megan Vance:
Facing the Exascale Energy Wall. IWIA 2010: 51-58 - [c49]Marco Ottavi
, Salvatore Pontarelli
, Erik DeBenedictis, Adelio Salsano, Peter M. Kogge, Fabrizio Lombardi:
High throughput and low power dissipation in QCA pipelines using Bennett clocking. NANOARCH 2010: 17-22 - [c48]Megan Vance, Peter M. Kogge:
Introducing mNUMA: an extended PGAS architecture. PGAS 2010: 6
2000 – 2009
- 2009
- [j17]Peter M. Kogge:
The Challenges of Petascale Architectures. Comput. Sci. Eng. 11(5): 10-16 (2009) - [j16]Timothy J. Dysart, Peter M. Kogge:
Organizing wires for reliability in magnetic QCA. ACM J. Emerg. Technol. Comput. Syst. 5(4): 19:1-19:10 (2009) - [j15]Timothy J. Dysart, Peter M. Kogge:
Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 507-516 (2009) - 2008
- [c47]Jay B. Brockman, Sheng Li, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi:
Design of a mask-programmable memory/multiplier array using G4-FET technology. DAC 2008: 337-338 - [c46]Timothy J. Dysart, Peter M. Kogge:
System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata. DFT 2008: 72-80 - [c45]Sheng Li, Shannon K. Kuntz, Peter M. Kogge, Jay B. Brockman:
Memory model effects on application performance for a lightweight multithreaded architecture. IPDPS 2008: 1-8 - 2007
- [j14]Richard C. Murphy, Peter M. Kogge:
On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications. IEEE Trans. Computers 56(7): 937-945 (2007) - [c44]Sarah E. Murphy, Erik DeBenedictis, Peter M. Kogge:
General floorplan for reversible quantum-dot cellular automata. Conf. Computing Frontiers 2007: 77-82 - [c43]Timothy J. Dysart, Peter M. Kogge:
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder. DFT 2007: 478-486 - [c42]Sheng Li, Amit Kashyap, Shannon K. Kuntz, Jay B. Brockman, Peter M. Kogge, Paul L. Springer, Gary Block:
A Heterogeneous Lightweight Multithreaded Architecture. IPDPS 2007: 1-8 - [c41]Srinivas Sridharan, Arun Rodrigues, Peter M. Kogge:
Evaluating synchronization techniques for light-weight multithreaded/multicore architectures. SPAA 2007: 57-58 - 2006
- [c40]Arun Rodrigues, Kyle B. Wheeler, Peter M. Kogge, Keith D. Underwood:
Fine-Grained Message Pipelining for Improved MPI Performance. CLUSTER 2006 - [c39]James F. Kramer, Matthias Scheutz, Jay B. Brockman, Peter M. Kogge:
Facing up to the Inevitable: Intelligent Error Recovery in Massively Parallel Processing in Memory Architectures. PDPTA 2006: 227-233 - [c38]Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp
, David E. Keyes, Peter H. Beckman:
Multi-core issues - Multi-Core for HPC: breakthrough or breakdown? SC 2006: 73 - [c37]Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood:
Poster reception - The structural simulation toolkit: exploring novel architectures. SC 2006: 157 - [c36]Erik DeBenedictis, David E. Keyes, Peter M. Kogge:
M06 - Issues for the future of supercomputing: impact of Moore's law and architecture on application performance. SC 2006: 220 - 2005
- [j13]Danny Z. Chen, Ovidiu Daescu, John Hershberger, Peter M. Kogge, Ningfang Mi, Jack Snoeyink
:
Polygonal path simplification with angle constraints. Comput. Geom. 32(3): 173-187 (2005) - [c35]Craig S. Lent, Sarah E. Frost, Peter M. Kogge:
Reversible computation with quantum-dot cellular automata (QCA). Conf. Computing Frontiers 2005: 403 - [c34]Richard C. Murphy, Arun Rodrigues, Peter M. Kogge, Keith D. Underwood:
The implications of working set analysis on supercomputing memory hierarchy design. ICS 2005: 332-340 - [c33]Alexei Kudriavtsev, Peter M. Kogge:
Generation of permutations for SIMD processors. LCTES 2005: 147-156 - 2004
- [c32]Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier:
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. DAC 2004: 363-368 - [c31]Michael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge:
Using Circuits and Systems-Level Research to Drive Nanotechnology. ICCD 2004: 302-309 - [c30]Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood:
Characterizing a new class of threads in scientific applications for high end supercomputers. ICS 2004: 164-174 - [c29]Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge:
Cache implications of aggressively pipelined high performance microprocessors. ISPASS 2004: 123-132 - [c28]Michael T. Niemier, Peter M. Kogge:
The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA. ISVLSI 2004: 3-10 - [c27]Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge:
A low cost, multithreaded processing-in-memory system. WMPI 2004: 16-22 - 2003
- [j12]Dmitry V. Ponomarev, Gurhan Kucuk
, Oguz Ergin
, Kanad Ghose, Peter M. Kogge:
Energy-efficient issue queue design. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 789-800 (2003) - [c26]Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Jay B. Brockman, Ron Brightwell, Keith D. Underwood:
Implications of a PIM Architectural Model for MPI. CLUSTER 2003: 259- - [c25]Peter M. Kogge:
The State of State. HPCA 2003: 266 - [c24]Sarah E. Frost, Arun Rodrigues, Charles A. Giefer, Peter M. Kogge:
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory. ISVLSI 2003: 19-28 - [c23]Gary H. Bernstein, Jay B. Brockman, Peter M. Kogge, Gregory L. Snider
, Barbara E. Walvoord:
From Bits to Chips: A Multidisciplinary Curriculum for Microelectronics System Design Education. MSE 2003: 95-97 - 2002
- [c22]Michael Thaddeus Niemier, Peter M. Kogge:
Teaching students computer architecture for new, nanotechnologies. WCAE 2002: 4 - [e1]Kanad Ghose, Patrick H. Madden, Vivek De, Peter M. Kogge:
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002. ACM 2002, ISBN 1-58113-462-2 [contents] - 2001
- [j11]Michael T. Niemier, Peter M. Kogge:
Problems in designing with QCAs: Layout = Timing. Int. J. Circuit Theory Appl. 29(1): 49-62 (2001) - [j10]Victor V. Zyuban, Peter M. Kogge:
Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Trans. Computers 50(3): 268-285 (2001) - [c21]Lilia Yerosheva, Shannon K. Kuntz, Peter M. Kogge, Jay B. Brockman:
A Microserver View of HTMT. IPDPS 2001: 3 - [c20]Michael T. Niemier, Peter M. Kogge:
Exploring and exploiting wire-level pipelining in emerging technologies. ISCA 2001: 166-177 - [c19]Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge:
Energy: efficient instruction dispatch buffer design for superscalar processors. ISLPED 2001: 237-242 - [c18]Shannon K. Kuntz, Richard C. Murphy, Michael T. Niemier, Jesús A. Izaguirre, Peter M. Kogge:
Petaflop Computing for Protein Folding. PP 2001 - [c17]Danny Z. Chen, Ovidiu Daescu, John Hershberger, Peter M. Kogge, Jack Snoeyink:
Polygonal path approximation with angle constraints. SODA 2001: 342-343 - 2000
- [c16]Michael T. Niemier, Michael J. Kontz, Peter M. Kogge:
A design of and design tools for a novel quantum dot based microprocessor. DAC 2000: 227-232 - [c15]Richard C. Murphy, Peter M. Kogge, Arun Rodrigues:
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. Intelligent Memory Systems 2000: 85-103 - [c14]Victor V. Zyuban, Peter M. Kogge:
Optimization of high-performance superscalar architectures for energy efficiency. ISLPED 2000: 84-89
1990 – 1999
- 1999
- [j9]Kanad Ghose, Kiran Raghavendra Desai, Peter M. Kogge:
Accelerating object-oriented applications using method lookup caches and register windowing. J. Syst. Archit. 45(12-13): 1023-1046 (1999) - [j8]Victor V. Zyuban, Peter M. Kogge:
Application of STD to latch-power estimation. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 111-115 (1999) - [c13]Lilia Yerosheva, Peter M. Kogge:
Prototyping Execution Models for HTMT Petaflop Machine in Java. CANPC 1999: 32-46 - [c12]Michael T. Niemier, Peter M. Kogge:
Logic in Wire: Using Quantum Dots to Implement a Microprocessor. Great Lakes Symposium on VLSI 1999: 118-121 - [c11]Michael T. Niemier, Peter M. Kogge:
Logic in wire: using quantum dots to implement a microprocessor. ICECS 1999: 1211-1215 - [c10]Jay B. Brockman, Peter M. Kogge, Thomas L. Sterling, Vincent W. Freeh, Shannon K. Kuntz:
Microservers: a new memory semantics for massively parallel computing. International Conference on Supercomputing 1999: 454-463 - [c9]Mary W. Hall
, Peter M. Kogge, Jefferey G. Koller, Pedro C. Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss, John J. Granacki, Jay B. Brockman, Apoorv Srivastava, William C. Athas, Vincent W. Freeh, Jaewook Shin, Joonseok Park:
Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture. SC 1999: 57 - 1998
- [c8]Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge:
Optimizing Data Scheduling on Processor-in-Memory Arrays. IPPS/SPDP 1998: 57-61 - [c7]Victor V. Zyuban, Peter M. Kogge:
The energy complexity of register files. ISLPED 1998: 305-310 - 1996
- [j7]Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter:
A parallel processing chip with embedded DRAM macros. IEEE J. Solid State Circuits 31(10): 1556-1559 (1996) - [c6]Kanad Ghose, Kiran Raghavendra Desai, Peter M. Kogge:
Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications. EUROMICRO 1996: 441- - 1995
- [c5]Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura
, Eric Retter:
Combined DRAM and logic chip for massively parallel systems. ARVLSI 1995: 4-16 - 1994
- [j6]Peter M. Kogge:
Preface. IBM J. Res. Dev. 38(2): 115-116 (1994) - [c4]Peter M. Kogge:
EXECUBE - A New Architecture for Scalable MPPs. ICPP (1) 1994: 77-84 - 1992
- [c3]Peter M. Kogge:
Declarative Computing: A Technology Driver. ARCS 1992: 1-17
1980 – 1989
- 1988
- [j5]Peter M. Kogge, John V. Oldfield, Mark R. Brule, Charles D. Stormon:
VLSI and rule-based systems. SIGARCH Comput. Archit. News 16(5): 52-65 (1988) - 1985
- [j4]Peter M. Kogge:
Function-based computing and parallelism: A review. Parallel Comput. 2(3): 243-253 (1985) - 1982
- [j3]Peter M. Kogge:
Am Architectural Trail to Threaded-Code Systems. Computer 15(3): 22-32 (1982)
1970 – 1979
- 1977
- [c2]Peter M. Kogge:
The Microprogramming of Pipelined Processors. ISCA 1977: 63-70 - 1974
- [j2]Peter M. Kogge:
Parallel Solution of Recurrence Problems. IBM J. Res. Dev. 18(2): 138-148 (1974) - 1973
- [j1]Peter M. Kogge, Harold S. Stone:
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations. IEEE Trans. Computers 22(8): 786-793 (1973) - [c1]Peter M. Kogge:
Maximal Rate Pipelined Solutions to Recurrance Problems. ISCA 1973: 71-76
Coauthor Index
aka: Michael Thaddeus Niemier
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