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2020 – today
- 2024
[j8]Suhyeong Choi, Jinwook Jung
, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon:
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1218-1231 (2024)- 2023
- [i1]Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon:
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement. CoRR abs/2304.13215 (2023)
2010 – 2019
- 2017
- [c8]Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi:
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. ISSCC 2017: 208-209 - 2011
- [c7]Chul-Hong Park, David Z. Pan, Kevin Lucas:
Exploration of VLSI CAD researches for early design rule evaluation. ASP-DAC 2011: 405-406 - 2010
- [j7]Soo-Han Choi, Young Hee Park, Chul-Hong Park, Sang Hoon Lee, Moon-Hyun Yoo, Jun Dong Cho, Gyu Tae Kim:
Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device. IEICE Trans. Electron. 93-C(5): 658-661 (2010) - [j6]Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 939-952 (2010) - [j5]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1070-1082 (2010)
2000 – 2009
- 2009
- [j4]Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
Lens aberration aware placement for timing yield. ACM Trans. Design Autom. Electr. Syst. 14(1): 16:1-16:26 (2009) - 2008
- [b1]Chul-Hong Park:
Lithography-driven design for manufacturing in nanometer- era VLSI. University of California, San Diego, USA, 2008 - [j3]Andrew B. Kahng, Chul-Hong Park, Xu Xu:
Fast Dual-Graph-Based Hotspot Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1635-1642 (2008) - [c6]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC 2008: 516-521 - [c5]Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout decomposition for double patterning lithography. ICCAD 2008: 465-472 - 2007
- [j2]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2144-2157 (2007) - 2006
- [j1]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu:
Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2747-2756 (2006) - [c4]Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
Lens aberration aware timing-driven placement. DATE 2006: 890-895 - 2005
- [c3]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
Detailed placement for improved depth of focus and CD control. ASP-DAC 2005: 343-348 - 2002
- [c2]Chul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong:
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond. ISQED 2002: 143-147 - 2000
- [c1]Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo:
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC. ISQED 2000: 81-86
Coauthor Index
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