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ORCIDDipanjan Sengupta
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2020 – today
- 2020
[i2]Mariano Tepper, Dipanjan Sengupta, Theodore L. Willke:
Procrustean Orthogonal Sparse Hashing. CoRR abs/2006.04847 (2020)
2010 – 2019
- 2019
- [c18]Guixiang Ma, Nesreen K. Ahmed
, Theodore L. Willke, Dipanjan Sengupta, Michael W. Cole, Nicholas B. Turk-Browne, Philip S. Yu:
Deep Graph Similarity Learning for Brain Data Analysis. CIKM 2019: 2743-2751 - 2018
- [j4]Probir Roy, Shuaiwen Leon Song, Sriram Krishnamoorthy, Abhinav Vishnu, Dipanjan Sengupta, Xu Liu:
NUMA-Caffe: NUMA-Aware Deep Learning Neural Networks. ACM Trans. Archit. Code Optim. 15(2): 24:1-24:26 (2018) - [i1]Guixiang Ma, Nesreen K. Ahmed, Theodore L. Willke, Dipanjan Sengupta, Michael W. Cole, Nicholas B. Turk-Browne, Philip S. Yu:
Similarity Learning with Higher-Order Proximity for Brain Network Analysis. CoRR abs/1811.02662 (2018) - 2017
- [c17]Dipanjan Sengupta, Shuaiwen Leon Song:
EvoGraph: On-the-Fly Efficient Mining of Evolving Graphs on GPU. ISC 2017: 97-119 - [c16]Dipanjan Sengupta, Yida Wang, Narayanan Sundaram, Theodore L. Willke:
High-Performance Incremental SVM Learning on Intel® Xeon Phi™ Processors. ISC 2017: 120-138 - 2016
- [b1]Dipanjan Sengupta:
System design principles for heterogeneous resource management and scheduling in accelerator-based systems. Georgia Institute of Technology, Atlanta, GA, USA, 2016 - [c15]Dipanjan Sengupta, Narayanan Sundaram, Xia Zhu, Theodore L. Willke, Jeffrey S. Young, Matthew Wolf, Karsten Schwan:
GraphIn: An Online High Performance Incremental Graph Processing Framework. Euro-Par 2016: 319-333 - 2015
- [c14]Dipanjan Sengupta, Kapil Agarwal, Shuaiwen Leon Song, Karsten Schwan:
GraphReduce: Large-Scale Graph Analytics on Accelerator-Based HPC Systems. IPDPS Workshops 2015: 604-609 - [c13]Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris:
Constructing stability-based clock gating with hierarchical clustering. PATMOS 2015: 97-102 - [c12]Dipanjan Sengupta, Shuaiwen Leon Song, Kapil Agarwal, Karsten Schwan:
GraphReduce: processing large-scale graphs on accelerator-based systems. SC 2015: 28:1-28:12 - [c11]Dipanjan Sengupta, Qi Wang, Haris Volos, Ludmila Cherkasova, Jun Li, Guilherme Magalhaes, Karsten Schwan:
A Framework for Emulating Non-Volatile Memory Systemswith Different Performance Characteristics. ICPE 2015: 317-320 - 2014
- [c10]Dipanjan Sengupta, Anshuman Goswami, Karsten Schwan, Krishna Pallavi:
Scheduling Multi-tenant Cloud Workloads on Accelerator-Based Systems. SC 2014: 513-524 - 2013
- [c9]Bao Le, Dipanjan Sengupta, Andreas G. Veneris:
Reviving erroneous stability-based clock-gating using partial Max-SAT. ASP-DAC 2013: 717-722 - [c8]Dipanjan Sengupta, Raghavendra Belapure, Karsten Schwan:
Multi-tenancy on GPGPU-based servers. VTDC@HPDC 2013: 3-10 - [c7]Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos:
Accelerating post silicon debug of deep electrical faults. IOLTS 2013: 61-66 - [c6]Dipanjan Sengupta, Erhan Ergin, Andreas G. Veneris:
Early detection of current hot spots in power gated designs. ISLPED 2013: 45-50 - 2012
- [j3]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov:
Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. 2(2): 58-70 (2012) - [c5]Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov:
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. ACM Great Lakes Symposium on VLSI 2012: 189-194 - 2011
- [c4]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh:
Sequence pair based voltage island floorplanning. IGCC 2011: 1-6
2000 – 2009
- 2009
- [j2]Dipanjan Sengupta, Resve A. Saleh:
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 316-326 (2009) - 2008
- [c3]Dipanjan Sengupta, Resve A. Saleh:
Application-driven floorplan-aware voltage island design. DAC 2008: 155-160 - [c2]Dipanjan Sengupta, Resve A. Saleh:
Supply voltage selection in Voltage Island based SoC design. SoCC 2008: 219-222 - 2007
- [j1]Dipanjan Sengupta, Resve A. Saleh:
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 183-189 (2007) - 2005
- [c1]Dipanjan Sengupta, Resve A. Saleh:
Power-Delay Metrics Revisited for 90nm CMOS Technology. ISQED 2005: 291-296
Coauthor Index
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