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ORCIDN. S. Nagaraj
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2000 – 2009
- 2009
[c27]Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork:
Moore's Law: another casualty of the financial meltdown? DAC 2009: 202-203- 2008
- [c26]Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh:
DFM in practice: hit or hype? DAC 2008: 898-899 - 2006
- [c25]Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj:
Optimizing Interconnect for Performance in Standard Cell Library. APCCAS 2006: 1280-1284 - [c24]Usha Narasimha, Binu Abraham, N. S. Nagaraj:
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. ISQED 2006: 795-800 - [c23]N. S. Nagaraj:
Interconnect Process Variations: Theory and Practice. VLSI Design 2006: 11 - [c22]Usha Narasimha, Anthony M. Hill, N. S. Nagaraj:
SmartExtract: Accurate Capacitance Extraction for SOC Designs. VLSI Design 2006: 786-789 - 2005
- [c21]N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill:
BEOL variability and impact on RC extraction. DAC 2005: 758-759 - [c20]N. S. Nagaraj:
Dealing with interconnect process variations. SLIP 2005: 39 - [c19]N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell:
The Impact of Inductance on Transients Affecting Gate Oxide Reliability. VLSI Design 2005: 709-713 - 2004
- [c18]Renuka Sindhgatta, Swaminathan Natarajan, Krishnakumar Pooloth, Colin Pinto, N. S. Nagaraj:
Autonomic Incident Manager for Enterprise Applications. GCC Workshops 2004: 642-649 - [c17]Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich:
A 800 MHz System-on-Chip for Wireless Infrastructure Applications. VLSI Design 2004: 381- - [c16]N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara:
Interconnect Modeling for Copper/Low-k Technologies. VLSI Design 2004: 425- - 2003
- [c15]N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell:
Benchmarks for Interconnect Parasitic Resistance and Capacitance. ISQED 2003: 163-168 - 2002
- [j1]Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal:
A 600-MHz VLIW DSP. IEEE J. Solid State Circuits 37(11): 1532-1544 (2002) - [c14]N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell:
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. ASP-DAC/VLSI Design 2002: 141 - 2001
- [c13]Narain Arora, N. S. Nagaraj:
Interconnect Modeling for Timing, Signal Integrity and Reliability. ISQED 2001: 13 - 2000
- [c12]N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang:
When bad things happen to good chips (panel session). DAC 2000: 736-737 - [c11]Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant:
Enabling DIR(Designing-In-Reliability) through CAD Capabilities. ISQED 2000: 151-156 - [c10]Steffen Rochel, N. S. Nagaraj:
Full-Chip Signal Interconnect Analysis for Electromigration Reliability. ISQED 2000: 337-340 - [c9]N. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das:
A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs. VLSI Design 2000: 370-375
1990 – 1999
- 1998
- [c8]N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone:
Taming Noise in Deep Submicron Digital Integrated Circuits (Panel). DAC 1998: 100-101 - [c7]N. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young:
A Practical Approach to Static Signal Electromigration Analysis. DAC 1998: 572-577 - 1997
- [c6]R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele:
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. ISPD 1997: 212-217 - 1994
- [c5]N. S. Nagaraj, Paul Krivacek, Mark Harward:
Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees. ISCAS 1994: 109-112 - 1993
- [c4]N. S. Nagaraj:
A New Optimizer for Performance Optimization of Analog Integrated Circuits. DAC 1993: 148-153 - [c3]N. S. Nagaraj:
A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing. ISCAS 1993: 2102-2105 - 1992
- [c2]N. S. Nagaraj:
OPSYN - OASYS Based Pseudosynthesis Tool. VLSI Design 1992: 117-123 - [c1]S. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand:
WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits. VLSI Design 1992: 297-302
Coauthor Index
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