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2010 – 2019
- 2013
[c4]Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Shohei Kawaguchi, Masaomi Sato, Toshio Sudo:
Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures. EMC Compo 2013: 142-146- [c3]Wataru Ichimura, Sho Kiyoshige, Masahiro Terasaki, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Toshio Sudo:
Anti-resonance peak frequency control by variable on-die capacitance. EMC Compo 2013: 171-174 - 2011
- [c2]Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda:
PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. 3DIC 2011: 1-2
2000 – 2009
- 2009
- [c1]Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka:
Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. 3DIC 2009: 1-4 - 2005
- [j2]Toshio Sudo:
Radiated Harmonics Characterization of CMOS Test Chip with On-Chip Decoupling Capacitance. IEICE Trans. Commun. 88-B(8): 3195-3199 (2005)
1990 – 1999
- 1995
- [j1]Toshio Sudo:
Present and future directions for multichip module technologies. IEEE J. Solid State Circuits 30(4): 436-442 (1995)
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