Plenary: Keynote Session

• 
  Emile H. L. Aarts, Raf Roovers: IC Design Challenges for Ambient Intelligence. 10002-10007
• 
  Andrea Cuomo: Semiconductor Challenges. 10008-10009

Topic: Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts

• 
  Menno Lindwer, Diana Marculescu, Twan Basten, Rainer Zimmermann, Radu Marculescu, Stefan Jung, Eugenio Cantatore: Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts. 10010-10017

Energy-Efficient Memory Systems

• 
  Alberto Macii, Enrico Macii, Massimo Poncino: Improving the Efficiency of Memory Partitioning by Address Clustering. 10018-10023
• 
  Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon: A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. 10024-10029
• 
  Peter Petrov, Alex Orailoglu: Power Efficiency through Application-Specific Instruction Memory Transformations. 10030-10035
• 
  Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida: Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. 10036-10043

Embedded Tutorial: Circuit, Platform Design and Test Challenges in Technologies Beyond 90nm

• 
  Bill Grundmann, Rajesh Galivanche, Sandip Kundu: Circuit and Platform Design Challenges in Technologies beyond 90nm. 10044-10049

Uncertainty

• 
  Li-Da Huang, Hung-Ming Chen, D. F. Wong: Global Wire Bus Configuration with Minimum Delay Uncertainty. 10050-10055
• 
  Hai Zhou: Timing Verification with Crosstalk for Transparently Latched Circuits. 10056-10061
• 
  Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. 10062-10067
• 
  Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman: Reduced Delay Uncertainty in High Performance Clock Distribution Networks. 10068-10075

Hot Topic: Scaling into Ambient Intelligence

• 
  Twan Basten, Luca Benini, Anantha Chandrakasan, Menno Lindwer, Jie Liu, Rex Min, Feng Zhao: Scaling into Ambient Intelligence. 10076-10083

Power-Aware Design and Synthesis

• 
  Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang: Masking the Energy Behavior of DES Encryption. 10084-10089
• 
  Dong Wu, Bashir M. Al-Hashimi, Petru Eles: Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems. 10090-10095
• 
  Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. 10096-10103

Test Data Compression

• 
  Wenjing Rao, Alex Orailoglu: Virtual Compression through Test Vector Stitching for Scan Based Designs. 10104-10109
• 
  Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch: Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. 10110-10115
• 
  Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre: A Technique for High Ratio LZW Compression. 10116-10121
• 
  Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski: Fast Computation of Data Correlation Using BDDs. 10122-10129

Operating System Abstraction and Targeting (Embedded Software Forum)

• 
  Andreas Gerstlauer, Haobo Yu, Daniel Gajski: RTOS Modeling for System Level Design. 10130-10135
• 
  Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi: Modeling and Integration of Peripheral Devices in Embedded Systems. 10136-10141
• 
  Fernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar: Systemic Embedded Software Generation from SystemC. 10142-10149

Analysis of Jitter and Noise for Analogue Systems and SD Modelling and Simulation

• 
  Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi: Noise Macromodel for Radio Frequency Integrated Circuits. 10150-10155
• 
  Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney: Approximation Approach for Timing Jitter Characterization in Circuit Simulators. 10156-10161
• 
  Ewout Martens, Georges G. E. Gielen: A Model of Computation for Continuous-Time ?-? Modulators. 10162-10167
• 
  R. Castro-López, Francisco V. Fernández, F. Medeiro, Ángel Rodríguez-Vázquez: Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages. 10168-10175

Hot Topic: Securing Your Mobile Appliance: New Challenges for the System Designer

• 
  Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater: Securing Mobile Appliances: New Challenges for the System Designer. 10176-10183

Scheduling and Analysis of Embedded Systems

• 
  Paul Pop, Petru Eles, Zebo Peng: Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. 10184-10189
• 
  Samarjit Chakraborty, Simon Künzli, Lothar Thiele: A General Framework for Analysing System Properties in Platform-Based Embedded System Designs. 10190-10195
• 
  George Logothetis, Klaus Schneider: Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration. 10196-10203
• 
  Bernhard Rinner, Martin Schmid, Reinhold Weiss: Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures. 10204-10211

Recent Advances in DFT and BIST

• 
  Muhammad Nummer, Manoj Sachdev: DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. 10212-10217
• 
  Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Extending JTAG for Testing Signal Integrity in SoCs. 10218-10223
• 
  Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty: EBIST: A Novel Test Generator with Built-In Fault Detection Capability. 10224-10229
• 
  Chunsheng Liu, Krishnendu Chakrabarty: A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. 10230-10237

Analogue and RF Modelling, Simulation and Optimisation

• 
  Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen: Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors. 10238-10243
• 
  Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney: A New Simulation Technique for Periodic Small-Signal Analysis. 10244-10249
• 
  Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen: Generalized Posynomial Performance Modeling. 10250-10255
• 
  Bart De Smedt, Georges G. E. Gielen: HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. 10256-10263

Architectural Level Synthesis

• 
  María C. Molina, José M. Mendías, Román Hermida: High-Level Allocation to Minimize Internal Hardware Wastage. 10264-10269
• 
  Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. 10270-10275
• 
  Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya: Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. 10276-10281
• 
  Kyeong Keol Ryu, Vincent John Mooney: Automated Bus Generation for Multiprocessor SoC Design. 10282-10289

Scheduling in Reconfigurable Computing

• 
  Herbert Walder, Marco Platzner: Online Scheduling for Block-Partitioned Reconfigurable Devices . 10290-10295
• 
  Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins: Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. 10296-10301
• 
  Sebastian Lange, Udo Kebschull: Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems. 10302-10309

Delay Testing and Diagnosis

• 
  Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara: A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. 10310-10315
• 
  Manan Syal, Michael S. Hsiao: A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. 10316-10321
• 
  Saravanan Padmanaban, Spyros Tragoudas: Non-Enumerative Path Delay Fault Diagnosis . 10322-10327
• 
  Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir: Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. 10328-10335

Embedded Tutorial: Embedded Operating Systems for SoC (Embedded Software Forum)

• 
  Sungjoo Yoo, Ahmed Amine Jerraya: Introduction to Hardware Abstraction Layers for SoC. 10336-10337
• 
  Vincent John Mooney: Hardware/Software Partitioning of Operating Systems. 10338-10339
• 
  Michel Sarlotte, Bernard Candaele, Jérôme Quévremont, D. Merel: Embedded Software in Digital AM-FM Chipset. 10340-10343

Networks-on-Chip

• 
  Terry Tao Ye, Luca Benini, Giovanni De Micheli: Packetized On-Chip Interconnect Communication Analysis for MPSoC. 10344-10349
• 
  Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. 10350-10355
• 
  Frank Gilbert, Michael J. Thul, Norbert Wehn: Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors . 10356-10363

System Level Modelling

• 
  Ingo Sander, Axel Jantsch, Zhonghai Lu: Development and Application of Design Transformations in ForSyDe. 10364-10369
• 
  Satnam Singh: System Level Specification in Lava. 10370-10375
• 
  Ashraf Salem: Formal Semantics of Synchronous SystemC. 10376-10381
• 
  Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta: Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated. 10382-10387
• 
  Alain Vachoux, Christoph Grimm, Karsten Einwich: SystemC-AMS Requirements, Design Objectives and Rationale. 10388-10395

Hot Topic: Runtime Reconfigurable Systems on Chip - An Industry Perspective

• 
  Kees A. Vissers: Parallel Processing Architectures for Reconfigurable Systems. 10396-10397
• 
  Bhusan Gupta, Michele Borgatti: Different Approaches to Add Reconfigurability in a SoC Architecture. 10398
• 
  Brandon Blodget, Scott McMillan, Patrick Lysaght: A Lightweight Approach for Embedded Reconfiguration of FPGAs. 10399-10401

Hot Topic: Creating Value Through Test

• 
  Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller: Creating Value Through Test. 10402-10409

Software Optimisation for Embedded Systems (Embedded Software Forum

• 
  Heiko Falk, Peter Marwedel: Control Flow Driven Splitting of Loop Nests at the Source Code Level . 10410-10415
• 
  Mahmut T. Kandemir, Guangyu Chen, Wei Zhang, Ibrahim Kolcu: Data Space Oriented Scheduling in Embedded Systems. 10416-10421
• 
  Satish Pillai, Margarida F. Jacome: Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling. 10422-10427
• 
  Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev: An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. 10428-10435

Global Approaches to Layout Synthesis

• 
  Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah: Time Budgeting in a Wireplanning Context. 10436-10441
• 
  Ruibing Lu, Cheng-Kok Koh: Interconnect Planning with Local Area Constrained Retiming. 10442-10447
• 
  Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu: A Novel Metric for Interconnect Architecture Performance. 10448-10455

Platform Design and IP Reuse Methods

• 
  Jianwen Zhu, Wai Sum Mong: Specification of Non-Functional Intellectual Property Components. 10456-10461
• 
  Yuan Xie, Wayne Wolf, Haris Lekatsas: Profile-Driven Selective Code Compression. 10462-10467
• 
  Chengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi: Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. 10468-10475

Panel: Reconfigurable Computing - Different Perspectives

• 
  Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang: Panel Title: Reconfigurable Computing - Different Perspectives. 10476-10477

Analogue and Defect-Oriented Testing

• 
  Doris Lupea, Udo Pursche, Hans-Joachim Jentschel: RF-BIST: Loopback Spectral Signature Analysis. 10478-10483
• 
  Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. 10484-10489
• 
  Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti: On Modeling Cross-Talk Faults. 10490-10495
• 
  Martin John Burbidge, Jim Tijou, Andrew Richardson: Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops. 10496-10503

Energy Aware Software Techniques (Embedded Software Forum)

• 
  Venkata Syam P. Rapaka, Diana Marculescu: Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications. 10504-10509
• 
  Mahmut T. Kandemir, Wei Zhang, Mustafa Karaköy: Runtime Code Parallelization for On-Chip Multiprocessors. 10510-10515
• 
  Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal: SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. 10516-10523

Interconnect Modelling and Signal Integrity

• 
  Ferran Martorell, Diego Mateo, Xavier Aragonès: Modeling and Evaluation of Substrate Noise Induced by Interconnects. 10524-10529
• 
  Makram M. Mansour, Amit Mehrotra: Model-Order Reduction Based on PRONY's Method. 10530-10535
• 
  Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero: Combined FDTD/Macromodel Simulation of Interconnected Digital Devices. 10536-10541
• 
  Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf: Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses. 10542-10549

System Level Simulation

• 
  Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya: Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. 10550-10555
• 
  Wei Qin, Sharad Malik: Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. 10556-10561
• 
  Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel: Instruction Set Emulation for Rapid Prototyping of SoCs . 10562-10569

Design Space Exploration for Reconfigurable Computing

• 
  Alberto La Rosa, Luciano Lavagno, Claudio Passerone: Hardware/Software Design Space Exploration for a Reconfigurable Processor. 10570-10575
• 
  João M. P. Cardoso, Markus Weinhardt: From C Programs to the Configure-Execute Model. 10576-10581
• 
  Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca: FPGA-Based Implementation of a Serial RSA Processor. 10582-10589

On-Line Testing and Self-Repair

• 
  Michael Nicolaidis, Nadir Achouri, Slimane Boutobza: Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair. 10590-10595
• 
  Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi: Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. 10596-10601
• 
  Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. 10602-10607
• 
  Martin Omaña, Daniele Rossi, Cecilia Metra: High Speed and Highly Testable Parallel Two-Rail Code Checker. 10608-10615

Hot Topic: Safe Automotive Software Development (Embedded Software Forum)

• 
  Ken Tindell, Hermann Kopetz, Fabian Wolf, Rolf Ernst: Safe Automotive Software Development. 10616-10623

Mixed-Signal Design Techniques

• 
  Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay: Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. 10624-10629
• 
  Carsten Wegener, Michael Peter Kennedy: Linear Model-Based Error Identification and Calibration for Data Converters. 10630-10635
• 
  Miquel Albiol, José Luis González, Eduard Alarcón: Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters. 10636-10641
• 
  Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. 10642-10649

Design Space Exploration

• 
  Arijit Ghosh, Tony Givargis: Analytical Design Space Exploration of Caches for Embedded Systems. 10650-10655
• 
  Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere: Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. 10656-10661
• 
  Laura Vanzago, Bishnupriya Bhattacharya, Joel Cambonie, Luciano Lavagno: Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform. 10662-10667
• 
  William Fornaciari, P. Micheli, Fabio Salice, L. Zampella: A First Step Towards Hw/Sw Partitioning of UML Specifications. 10668-10673
• 
  Yannick Le Moullec, Nahla Ben Amor, Jean-Philippe Diguet, Mohamed Abid, Jean Luc Philippe: Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. 10674-10681

Low Power Architectures

• 
  Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Energy Estimation for Extensible Processors. 10682-10687
• 
  Jingcao Hu, Radu Marculescu: Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. 10688-10693
• 
  Wei-Chung Cheng, Massoud Pedram: Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface. 10694-10699
• 
  Hunsoo Choo, Khurram Muhammad, Kaushik Roy: MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. 10700-10705
• 
  Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi: Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. 10706-10713

System-on-Chip Testing

• 
  Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Low-Cost Software-Based Self-Testing of RISC Processor Cores. 10714-10719
• 
  Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. 10720-10725
• 
  Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Test Data Compression: The System Integrator's Perspective. 10726-10731
• 
  Zahra Sadat Ebadi, André Ivanov: Time Domain Multiplexed TAM: Implementation and Comparison. 10732-10737
• 
  Sandeep Kumar Goel, Erik Jan Marinissen: Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. 10738-10741
• 
  Qiang Xu, Nicola Nicolici: Delay Fault Testing of Core-Based Systems-on-a-Chi. 10744-10752

Synthesis and Analysis of Digital Circuits

• 
  Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. 10752-10757
• 
  Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combination of Lower Bounds in Exact BDD Minimization. 10758-10763
• 
  Ana T. Freitas, Arlindo L. Oliveira: Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation. 10764-10769
• 
  Ulrich Seidl, Klaus Eckl, Frank M. Johannes: Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information. 10770-10777

Embedded System Architectures (Embedded Software Forum)

• 
  Amit Agarwal, Kaushik Roy, T. N. Vijaykumar: Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. 10778-10783
• 
  G. Surendra, Subhasis Banerjee, S. K. Nandy: Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. 10784-10789
• 
  Tudor Dumitras, Radu Marculescu: On-Chip Stochastic Communication. 10790-10795
• 
  Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Ismail Kadayif: An Integrated Approach for Improving Cache Behavior. 10796-10801
• 
  Newton Cheung, Jörg Henkel, Sri Parameswaran: Rapid Configuration and Instruction Selection for an ASIP: A Case Study. 10802-10809

Specification and Verification in Action

• 
  Yakov Novikov: Local Search for Boolean Relations on the Basis of Unit Propagation. 10810-10815
• 
  Amit Goel, Randal E. Bryant: Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis. 10816-10821
• 
  Shuo Sheng, Michael S. Hsiao: Efficient Preimage Computation Using A Novel Success-Driven ATPG. 10822-10827
• 
  Abhik Roychoudhury, Tulika Mitra, S. R. Karri: Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol. 10828-10833
• 
  Avi Ziv: Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions . 10834-10841

Hot Topic: RF Design Technology for Highly Integrated Communication Systems

• 
  Reimund Wittmann, Jürgen Hartung, Hans-Joachim Wassener, Günther Tränkle, Michael Schröter: Hot Topic Session: RF Design Technology for Highly Integrated Communication Systems. 10842-10849

Zoning Chip Estate

• 
  Kai Wang, Malgorzata Marek-Sadowska: Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. 10850-10855
• 
  Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. 10856-10861
• 
  Ryon M. Smey, Bill Swartz, Patrick H. Madden: Crosstalk Reduction in Area Routing. 10862-10867
• 
  Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng: Area Fill Generation With Inherent Data Volume Reduction. 10868-10875

Panel: Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

• 
  Heinz-Joseph Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel: Transaction Based Design: Another Buzzword or the Solution to a Design Problem? 10876-10879

Trust in SAT-Based Verification?

• 
  Lintao Zhang, Sharad Malik: Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. 10880-10885
• 
  Evguenii I. Goldberg, Yakov Novikov: Verification of Proofs of Unsatisfiability for CNF Formulas. 10886-10891
• 
  Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang: A Circuit SAT Solver With Signal Correlation Guided Learning. 10892-10897
• 
  Gianpiero Cabodi, Sergio Nocco, Stefano Quer: Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals. 10898-10905

Transformations for Real-Time Software (Embedded Software Forum)

• 
  Victor De La Luz, Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer: Generalized Data Transformations for Enhancing Cache Behavior. 10906-10911
• 
  Pramote Kuacharoen, Vincent John Mooney, Vijay K. Madisetti: Software Streaming via Block Streaming. 10912-10917
• 
  Ying Zhang, Krishnendu Chakrabarty: Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems. 10918-10925

Synthesis Tools for Asynchronous Circuits

• 
  Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev: Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design. 10926-10931
• 
  Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev: STG Optimisation in the Direct Mapping of Asynchronous Circuits . 10932-10939

Collaborative Design and WWW-Based Tools

• 
  Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner: Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. 10940-10945
• 
  Wolfgang Müller, Tim Schattkowsky, Heinz-Josef Eikerling, Jan Wegner: Dynamic Tool Integration in Heterogeneous Computer Networks. 10946-10953

Performance Optimisation in Hardware/Software Codesign

• 
  Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas: Layered, Multi-Threaded, High-Level Performance Design. 10954-10959
• 
  Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles: A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities. 10960-10965
• 
  Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl: Processor/Memory Co-Exploration on Multiple Abstraction Levels. 10966-10973

Dynamic Resource Management for Reconfigurable Systems

• 
  Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira: Run-Time Management of Logic Resources on Reconfigurable Systems. 10974-10979
• 
  Michael Dales: Managing a Reconfigurable Processor in a General Purpose Workstation Environment. 10980-10985
• 
  Jean-Yves Mignolet, Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins: Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. 10986-10993

Advances in Test Pattern Generation

• 
  Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira: RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. 10994-10999
• 
  Irith Pomeranz, Sudhakar M. Reddy: A New Approach to Test Generation and Test Compaction for Scan Circuits. 11000-11005
• 
  Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero: Fully Automatic Test Program Generation for Microprocessor Cores. 11006-11011
• 
  Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the Characterization of Hard-to-Detect Bridging Faults. 11012-11019

Analogue and Digital Simulation

• 
  Yu-Min Lee, Charlie Chung-Ping Chen: The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . 11020-11025
• 
  Zhong Wang, Jianwen Zhu: Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. 11026-11031
• 
  Márta Rencz, Vladimir Székely, András Poppe: A Fast Algorithm for the Layout Based Electro-Thermal Simulation. 11032-11037
• 
  Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi: Platform-Based Testbench Generation. 11038-11045

Low Power Software (Embedded Software Forum)

• 
  Tat Kee Tan, Anand Raghunathan, Niraj K. Jha: Software Architectural Transformations: A New Approach to Low Energy Embedded Software. 11046-11051
• 
  Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu: Dynamic Functional Unit Assignment for Low Power. 11052-11057
• 
  Mahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang: Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy. 11058-11063
• 
  Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau: Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. 11064-11069

Application Specific Memory Synthesis

• 
  Erik Brockmeyer, Miguel Miranda, Henk Corporaal, Francky Catthoor: Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations. 11070-11075
• 
  Sambuddhi Hettiaratchi, Peter Y. K. Cheung: Mesh Partitioning Approach to Energy Efficient Data Layout. 11076-11081
• 
  Mahesh Mamidipaka, Nikil D. Dutt: On-chip Stack Based Memory Organization for Low Power Embedded Architectures. 11082-11089

CAD for Analogue Design, Design Methodologies and Physical Design

• 
  Martin Vogels, Georges G. E. Gielen: Figure of Merit Based Selection of A/D Converters. 11090-11091
• 
  Oliver Kraus, Martin Padeffke: XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines. 11092-11093
• 
  Johnson S. Kin, José Luis Pino: Multithreaded Synchronous Data Flow Simulation. 11094-11095
• 
  Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese: PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. 11096-11097
• 
  Simona Doboli, Gaurav Gothoskar, Alex Doboli: Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering. 11098-11099
• 
  Abhijit K. Deb, Johnny Öberg, Axel Jantsch: Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology. 11100-11101
• 
  Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. 11102-11103
• 
  Wonjoon Choi, Kia Bazargan: Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. 11104-11105
• 
  Alessandro Girardi, Sergio Bampi: LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks. 11106-11107
• 
  Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram: Symbolic Analysis of Nonlinear Analog Circuits. 11108-11109
• 
  Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich: Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. 11110-11111
• 
  Seung Hoon Choi, Kaushik Roy: A New Crosstalk Noise Model for DOMINO Logic Circuits. 11112-11113
• 
  Li Ding, Pinaki Mazumder: Modeling Noise Transfer Characteristic of Dynamic Logic Gates. 11114-11117

Reconfigurable Computing and Systems Design

• 
  Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit: Heterogeneous Programmable Logic Block Architectures. 11118-11119
• 
  Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. 11120-11121
• 
  Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans: Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. 11122-11123
• 
  Michèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol: Mapping Applications to an FPFA Tile. 11124-11125
• 
  Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch: Load Distribution with the Proximity Congestion Awareness in a Network on Chip. 11126-11127
• 
  Adrijean Andriahantenaina, Alain Greiner: Micro-Network for SoC: Implementation of a 32-Port SPIN network. 11128-11129
• 
  Achim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann: A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems. 11130-11131
• 
  Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto: Library Functions Timing Characterization for Source-Level Analysis. 11132-11133
• 
  Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. 11134-11135
• 
  S. F. Nielsen, Jan Madsen: Power Constrained High-Level Synthesis of Battery Powered Digital Systems. 11136-11137
• 
  Bilge Saglam Akgul, Vincent John Mooney III: PARLAK: Parametrized Lock Cache Generator. 11138-11139
• 
  Tom J. Kazmierski, Xing Q. Yang: A Secure Web-Based Framework for Electronic System Level Design. 11140-11143

Low Power Design and Estimation, Verification and Testing

• 
  Pieter Op de Beeck, C. Ghez, Erik Brockmeyer, Miguel Miranda, Francky Catthoor, Geert Deconinck: Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor. 11144-11145
• 
  Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De: Compiler Support for Reducing Leakage Energy Consumption. 11146-11147
• 
  Peng Rong, Massoud Pedram: An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries. 11148-11149
• 
  Jiong Luo, Li-Shiuan Peh, Niraj K. Jha: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. 11150-11151
• 
  MingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. 11152-11153
• 
  Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli: Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. 11154-11155
• 
  Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Using RTL Statespace Information and State Encoding for Induction Based Property Checking. 11156-11157
• 
  Enric Pastor, Marco A. Peña: Combining Simulation and Guided Traversal for the Verification of Concurrent Systems. 11158-11159
• 
  Naran Sirisantana, Kaushik Roy: Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. 11160-11161
• 
  Steffen Tarnick: Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes. 11162-11163
• 
  Petros Drineas, Yiorgos Makris: Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees. 11164-11167

System Level Design and Specification and Testing Techniques

• 
  Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien: SAT-Based Techniques in System Synthesis. 11168-11169
• 
  Christoph Grimm, Christian Meise, Wilhelm Heupke, Klaus Waldschmidt: Refinement of Mixed-Signal Systems with SystemC. 11170-11171
• 
  Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet: Polychrony for Refinement-Based Design. 11172-11173
• 
  Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. 11174-11175
• 
  Ivo Schanstra, A. J. van de Goor: Consequences of RAM Bitline Twisting for Test Coverage. 11176-11177
• 
  Francesco Corsi, Cristoforo Marzocca, Gianvito Matarrese: An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme. 11178-11179
• 
  Hideyuki Ichihara, Tomoo Inoue: Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG. 11180-11181
• 
  Ondrej Novák: Comparison of Test Pattern Decompression Techniques. 11182-11183
• 
  Ilia Polian, Bernd Becker, Sudhakar M. Reddy: Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. 11184-11185
• 
  Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Based on Output Dependence. 11186-11187
• 
  Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty: A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. 11188-11190

Design Case Studies

• 
  Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo: Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. 20002-20007
• 
  Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. 20008-20013
• 
  George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis: Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. 20014-20019
• 
  Alex Panato, Marcelo Barcelos, Ricardo Augusto da Luz Reis: A Low Device Occupation IP to Implement Rijndael Algorithm. 20020-20025
• 
  Marco Caldari, Massimo Conti, Massimo Coppola, Stephane Curaba, Lorenzo Pieralisi, Claudio Turchetti: Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0. 20026-20031
• 
  Marco Caldari, Massimo Conti, Massimo Coppola, Paolo Crippa, Simone Orcioni, Lorenzo Pieralisi, Claudio Turchetti: System-Level Power Analysis Methodology Applied to the AMBA AHB Bus. 20032-20039

Embedded Operating Systems for SoC (Embedded Software Forum)

• 
  S. Glaeson, E. Petit: Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets. 20040
• 
  Monica Besana, Michele Borgatti: Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study. 20041-20044
• 
  Marek Jersak, Kai Richter, Rolf Ernst, Jörn-Christian Braam, Zheng-Yu Jiang, Fabian Wolf: Formal Methods for Integration of Automotive Software. 20045-20050
• 
  Frédéric Pétrot, Pascal Gomez: Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect. 20051-20056
• 
  B. Nicolescu, Raoul Velazco: Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results. 20057-20063

Hot Topic: Network Processing Key Technologies and Architectural Components

• 
  Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane: Network Processing Challenges and an Experimental NPU Platform. 20064-20069
• 
  Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino: SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. 20070-20073
• 
  Naresh Soni, Nick Richardson, Lun Bin Huang, Suresh Rajgopal, George Vlantis: NPSE: A High Performance Network Packet Search Engine. 20074-20081

SystemC Based Design

• 
  Koji Ara, Kei Suzuki: A Proposal for Transaction-Level Verification with Component Wrapper Language. 20082-20087
• 
  Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates: Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard. 20088-20094
• 
  Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene: A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification. 20095-20100
• 
  Massimo Bombana, Francesco Bruschi: SystemC-VHDL Co-Simulation and Synthesis in the HW Domain. 20101-20105
• 
  Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia: IPSIM: SystemC 3.0 Enhancements for Communication Refinement. 20106-20111
• 
  Francesco Bruschi, Fabrizio Ferrandi: Synthesis of Complex Control Structures from Behavioral SystemC Models. 20112-20119

Embedded Software Design and Implementation (Embedded Software Forum)

• 
  Imed Moussa, Thierry Grellier, Giang Nguyen: Exploring SW Performance Using SoC Transaction-Level Modeling. 20120-20125
• 
  Marco Göltze: A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices. 20126-20131
• 
  Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh: Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. 20132-20137
• 
  Shinya Honda, Hiroaki Takada: Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. 20138-20143
• 
  Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández: Interactive Ray Tracing on Reconfigurable SIMD MorphoSys. 20144-20149
• 
  Stephen Jan, Paolo de Dios, Stephen A. Edwards: Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development. 20150-20157

Design Exploration Methodologies

• 
  Johan Lilius, Dragos Truscan, Seppo Virtanen: Fast Evaluation of Protocol Processor Architectures for IPv6 Routing. 20158-20163
• 
  Silvia Brini, Doha Benjelloun, Fabien Castanier: A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems. 20164-20169
• 
  Sharath Kodase, Shige Wang, Kang G. Shin: Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints. 20170-20175
• 
  Osamu Ogawa, Sylvain Bayon de Noyer, Pascal Chauvet, Katsuya Shinohara, Yoshiharu Watanabe, Hiroshi Niizuma, Takayuki Sasaki, Yuji Takai: A Practical Approach for Bus Architecture Optimization at Transaction Level. 20176-20181
• 
  Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria: Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture. 20182-20187
• 
  Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino: Estimation of Bus Performance for a Tuplespace in an Embedded Architecture. 20188-20195

Design Methodologies

• 
  Árpád Bürmen, Janez Puhan, Tadej Tuma: Defining Cost Functions for Robust IC Design and Optimization. 20196-20201
• 
  Martin Schrader, Roderick McConnell: SoC Design and Test Considerations. 20202-20207
• 
  Bernard Laurent, Thierry Karger: A System to Validate and Certify Soft and Hard IP. 20208-20213
• 
  Marco Caldari, Massimo Conti, Paolo Crippa, Giuliano Marozzi, Fabio Di Gennaro, Simone Orcioni, Claudio Turchetti: SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel. 20214-20219
• 
  François Rémond, Pierre Bricaud: Set Top Box SoC Design Methodology at STMicroelectronics. 20220-20223
• 
  Fotis Andritsopoulos, C. Charopoulos, Gregory Doumenis, Fotis Karoubalis, Yannis Mitsos, F. Petreas, Ioanna Theologitou, Stylianos Perissakis, Dionisios I. Reisis: Verification of a Complex SoC: The PRO3 Case-Study. 20224-20231

System Level Design Case Studies

• 
  Leonardo Mangeruca, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Andrea Pierantoni, Michele Pennese: System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain. 20232-20237
• 
  Matjaz Verderber, Andrej Zemva, Damjan Lampret: HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder. 20238-20243
• 
  Jürgen Helmschmidt, Eberhard Schüler, Prashant Rao, Sergio Rossi, Serge di Matteo, Rainer Bonitz: Reconfigurable Signal Processing in Wireless Terminals. 20244-20249
• 
  Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin: A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. 20250-20255
• 
  Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer: Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. 20256-20261
• 
  Alessandro Pirola: A Solution for Hardware Emulation of Non Volatile Memory Macrocells. 20262-20267

Analogue and Mixed Signal Methodology Design

• 
  Rami Ahola, Daniel Wallner, Marius Sida: Bluetooth Transceiver Design with VHDL-AMS. 20268-20273
• 
  Pierluigi Daglio, Carlo Roma: A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies. 20274-20279
• 
  Ayman Mounir, Ahmed Mostafa, Maged Fikry: Automatic Behavioural Model Calibration for Efficient PLL System Verification. 20280-20285
• 
  Uwe Knöchel, Thomas Markwirth, Jürgen Hartung, Ralf Kakerow, Radhakrishna Atukula: Verification of the RF Subsystem within Wireless LAN System Level Simulation. 20286-20291
• 
  Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, Richard B. Brown: A Top-Down Microsystems Design Methodology and Associated Challenges . 20292-20296
• 
  Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud Magdy, Noha Hassan, Noha Soliman, Sami Moussa: Synthesis of CMOS Analog Cells Using AMIGO. 20297-20302

last updated on Wed May 22 02:49:00 2013 by the dblp team
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