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ORCIDMartin John Burbidge
Person information
- affiliation: Lancaster University, Centre for Microsystems Engineering, UK
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2000 – 2009
- 2007
[j5]Martin John Burbidge, Jim Tijou:
Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods. Integr. 40(2): 133-148 (2007)- 2006
- [j4]Kostas Georgopoulos, Andreas Lechner, Martin John Burbidge, Andrew Richardson
:
Investigation into the Use of Hybrid Solutions for SigmaDelta A/D Converter Testing. J. Electron. Test. 22(4-6): 359-370 (2006) - [c4]Martin John Burbidge, Ian Andrew Grout:
Evolution of a Remote Access Facility for a PLL Measurement Course. e-Science 2006: 141 - 2005
- [j3]Martin John Burbidge:
Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods. J. Electron. Test. 21(3): 267-281 (2005) - [j2]Ian Andrew Grout, Jason Murphy, Martin John Burbidge, George Bell, Avril E. Manners:
Development of a Remote Access Facility for a PLL Test Course. Int. J. Online Eng. 1(2) (2005) - 2003
- [j1]Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew Richardson:
Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's. J. Electron. Test. 19(4): 481-490 (2003) - [c3]Martin John Burbidge, Jim Tijou, Andrew Richardson:
Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops. DATE 2003: 10496-10503 - 2002
- [c2]Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew M. D. Richardson:
Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's. ETW 2002: 95-102 - 2001
- [c1]Andreas Lechner, Martin John Burbidge, Andrew Richardson, B. Hermes:
3DB Challange for DfT, DfM, DOT & BIST Integration into Analogue and Mixed Signal ICs. LATW 2001: 194-199
Coauthor Index
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