"Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations ..."

Naran Sirisantana, Kaushik Roy (2003)

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DOI: 10.1109/DATE.2003.10131

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Naran Sirisantana, Kaushik Roy:
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE 2003: 11160-11161

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