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ORCIDSharad Malik
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- affiliation: Princeton University, NJ, USA
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2020 – today
- 2024
[j67]Mengjia Yan
, Thomas Bourgeat, Sharad Malik:
Formal Verification for Secure Processors: A Guide for Computer Architects. Computer 57(10): 138-143 (2024)- [j66]Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Gus Henry Smith, Thierry Tambe, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik:
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface. ACM Trans. Design Autom. Electr. Syst. 29(2): 35:1-35:25 (2024) - [c196]Yi Li, Aarti Gupta, Sharad Malik:
Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators. ASPDAC 2024: 908-914 - [i8]Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan:
RTL Verification for Secure Speculation Using Contract Shadow Logic. CoRR abs/2407.12232 (2024) - 2023
- [j65]Qi Nie, Sharad Malik:
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks. ACM Trans. Design Autom. Electr. Syst. 28(3): 40:1-40:36 (2023) - [j64]Huaixi Lu, Yue Xing, Aarti Gupta, Sharad Malik:
SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications. ACM Trans. Design Autom. Electr. Syst. 28(6): 89:1-89:24 (2023) - [c195]Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin:
Security Verification of Low-Trust Architectures. CCS 2023: 945-959 - [c194]Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. DAC 2023: 1-4 - [i7]Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin:
Security Verification of Low-Trust Architectures. CoRR abs/2309.00181 (2023) - [i6]Yi Li, Aarti Gupta, Sharad Malik:
Combined Scheduling, Memory Allocation and Tensor Replacement for Minimizing Off-Chip Data Accesses of DNN Accelerators. CoRR abs/2311.18246 (2023) - 2022
- [c193]Yue Xing, Aarti Gupta, Sharad Malik:
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. ASP-DAC 2022: 154-159 - [c192]Yu Zeng, Aarti Gupta, Sharad Malik:
Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators. DATE 2022: 460-465 - [c191]Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik:
Compositional Verification Using a Formal Component and Interface Specification. ICCAD 2022: 72:1-72:9 - [c190]Qinhan Tan, Aarti Gupta, Sharad Malik:
Usage-Based RTL Subsetting for Hardware Accelerators. ICCAD 2022: 73:1-73:9 - [i5]Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik:
Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface. CoRR abs/2203.00218 (2022) - 2021
- [j63]Lauren Biernacki, Mark Gallagher, Zhixing Xu, Misiker Tadesse Aga, Austin Harris, Shijia Wei, Mohit Tiwari, Baris Kasikci, Sharad Malik, Todd M. Austin:
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses. ACM J. Emerg. Technol. Comput. Syst. 17(3): 42:1-42:38 (2021) - [c189]Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik:
Leveraging Processor Modeling and Verification for General Hardware Modules. DATE 2021: 1130-1135 - [c188]Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD 2021: 1-9 - [c187]Hongce Zhang, Aarti Gupta, Sharad Malik:
Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. VMCAI 2021: 325-349 - [p10]João Marques-Silva, Inês Lynce, Sharad Malik:
Conflict-Driven Clause Learning SAT Solvers. Handbook of Satisfiability 2021: 133-182 - 2020
- [j62]Qi Nie, Sharad Malik:
MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1875-1888 (2020) - [c186]Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, Sharad Malik:
Synthesizing Environment Invariants for Modular Hardware Verification. VMCAI 2020: 202-225
2010 – 2019
- 2019
- [j61]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. ACM Trans. Design Autom. Electr. Syst. 24(1): 10:1-10:24 (2019) - [j60]Burçin Çakir, Sharad Malik:
Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings. ACM Trans. Design Autom. Electr. Syst. 24(5): 50:1-50:19 (2019) - [c185]Sharad Malik, Pareesa Ameneh Golnari:
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration. ASAP 2019: 67-70 - [c184]Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd M. Austin:
Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. ASPLOS 2019: 469-484 - [c183]Qi Nie, Sharad Malik:
SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication. ISCAS 2019: 1-5 - [c182]Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. TACAS (1) 2019: 351-357 - [i4]Pareesa Ameneh Golnari, Sharad Malik:
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (long version). CoRR abs/1906.00327 (2019) - 2018
- [j59]Pramod Subramanyan, Bo-Yuan Huang, Yakir Vizel, Aarti Gupta, Sharad Malik:
Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1692-1705 (2018) - [j58]Burçin Çakir, Sharad Malik:
Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs. ACM Trans. Design Autom. Electr. Syst. 23(4): 50:1-50:19 (2018) - [c181]Qi Nie, Sharad Malik:
MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. ASP-DAC 2018: 446-451 - [c180]Weikun Yang, Yakir Vizel, Pramod Subramanyan, Aarti Gupta, Sharad Malik:
Lazy Self-composition for Security Verification. CAV (2) 2018: 136-156 - [c179]Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik:
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. DAC 2018: 91:1-91:6 - [c178]Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik:
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. FMCAD 2018: 1-10 - [c177]Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari:
Vulnerability-tolerant secure architectures. ICCAD 2018: 46 - [c176]Yue Xing, Bo-Yuan Huang, Aarti Gupta, Sharad Malik:
A formal instruction-level GPU model for scalable verification. ICCAD 2018: 130 - [p9]João Marques-Silva, Sharad Malik:
Propositional SAT Solving. Handbook of Model Checking 2018: 247-275 - [i3]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. CoRR abs/1801.01114 (2018) - 2017
- [j57]Pareesa Ameneh Golnari, Yavuz Yetim, Margaret Martonosi, Yakir Vizel, Sharad Malik:
PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees. ACM J. Emerg. Technol. Comput. Syst. 13(3): 43:1-43:29 (2017) - [c175]Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik:
Malware detection using machine learning based analysis of virtual memory access patterns. DATE 2017: 169-174 - [c174]Pareesa Ameneh Golnari, Sharad Malik:
Evaluating matrix representations for error-tolerant computing. DATE 2017: 1659-1662 - [c173]Yakir Vizel, Alexander Nadel, Sharad Malik:
Solving linear arithmetic with SAT-based model checking. FMCAD 2017: 47-54 - [c172]Zhixing Xu, Aarti Gupta, Sharad Malik:
Trace-based Analysis of Memory Corruption Malware Attacks. Haifa Verification Conference 2017: 67-82 - [c171]Yakir Vizel, Alexander Nadel, Sharad Malik:
Solving Constraints over Bit-Vectors with SAT-based Model Checking. SMT 2017: 101-107 - [c170]Yakir Vizel, Arie Gurfinkel, Sharon Shoham, Sharad Malik:
IC3 - Flipping the E in ICE. VMCAI 2017: 521-538 - 2016
- [j56]Alexander Ivrii, Sharad Malik, Kuldeep S. Meel, Moshe Y. Vardi:
On computing minimal independent support and its applications to sampling and counting. Constraints An Int. J. 21(1): 41-58 (2016) - [j55]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Model checking unbounded concurrent lists. Int. J. Softw. Tools Technol. Transf. 18(4): 375-391 (2016) - [c169]Kuldeep S. Meel, Moshe Y. Vardi, Supratik Chakraborty, Daniel J. Fremont, Sanjit A. Seshia, Dror Fried, Alexander Ivrii, Sharad Malik:
Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. AAAI Workshop: Beyond NP 2016 - [c168]Sharad Malik, Pramod Subramanyan:
Invited - Specification and modeling for systems-on-chip security verification. DAC 2016: 66:1-66:6 - [c167]Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, Jason M. Fung:
Verifying information flow properties of firmware using symbolic execution. DATE 2016: 337-342 - 2015
- [j54]Yakir Vizel, Georg Weissenbacher, Sharad Malik:
Boolean Satisfiability Solvers and Their Applications in Model Checking. Proc. IEEE 103(11): 2021-2035 (2015) - [c166]Yavuz Yetim, Sharad Malik, Margaret Martonosi:
CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution. ASPLOS 2015: 311-323 - [c165]Yakir Vizel, Arie Gurfinkel, Sharad Malik:
Fast Interpolating BMC. CAV (1) 2015: 641-657 - [c164]Sunha Ahn, Sharad Malik, Aarti Gupta:
Completeness bounds and sequentialization for model checking of interacting firmware and hardware. CODES+ISSS 2015: 202-211 - [c163]Burçin Çakir, Sharad Malik:
Hardware Trojan detection for gate-level ICs using signal correlation based clustering. DATE 2015: 471-476 - [c162]Charlie Shucheng Zhu, Sharad Malik:
Optimizing dynamic trace signal selection using machine learning and linear programming. DATE 2015: 1289-1292 - [c161]Sharad Malik:
Detecting Hardware Trojans: A Tale of Two Techniques. FMCAD 2015: 6 - [c160]Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik:
Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. FMCAD 2015: 160-167 - [c159]Pramod Subramanyan, Sayak Ray, Sharad Malik:
Evaluating the security of logic encryption algorithms. HOST 2015: 137-143 - [c158]Ameneh Golnari, Yakir Vizel, Sharad Malik:
Error-Tolerant Processors: Formal Specification and Verification. ICCAD 2015: 286-293 - [i2]Kuldeep S. Meel, Moshe Y. Vardi, Supratik Chakraborty, Daniel J. Fremont, Sanjit A. Seshia, Dror Fried, Alexander Ivrii, Sharad Malik:
Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. CoRR abs/1512.06633 (2015) - 2014
- [j53]Pramod Subramanyan, Nestan Tsiskaridze, Wenchao Li, Adrià Gascón, Wei Yang Tan, Ashish Tiwari, Natarajan Shankar, Sanjit A. Seshia, Sharad Malik:
Reverse Engineering Digital Circuits Using Structural and Functional Analyses. IEEE Trans. Emerg. Top. Comput. 2(1): 63-80 (2014) - [c157]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. ATVA 2014: 330-347 - [c156]Sunha Ahn, Sharad Malik:
Automated firmware testing using firmware-hardware interaction patterns. CODES+ISSS 2014: 25:1-25:10 - [c155]Shuyuan Zhang, Franjo Ivancic, Cristian Lumezanu, Yifei Yuan, Aarti Gupta, Sharad Malik:
An Adaptable Rule Placement for Software-Defined Networks. DSN 2014: 88-99 - [c154]Adrià Gascón, Pramod Subramanyan, Bruno Dutertre, Ashish Tiwari, Dejan Jovanovic, Sharad Malik:
Template-based circuit understanding. FMCAD 2014: 83-90 - [c153]Roderick Bloem, Sharad Malik, Matthias Schlaipfer, Georg Weissenbacher:
Reduction of Resolution Refutations and Interpolants via Subsumption. Haifa Verification Conference 2014: 188-203 - [c152]Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Silicon fault diagnosis using sequence interpolation with backbones. ICCAD 2014: 348-355 - [c151]Shuyuan Zhang, Sharad Malik, Sanjai Narain, Laurent Vanbever:
In-Band Update for Network Routing Policy Migration. ICNP 2014: 356-361 - [c150]Sayak Ray, Sharad Malik:
Effective abstraction for response proof of communication fabrics. NOCS 2014: 188-189 - [c149]Ryan Beckett, Xuan Kelvin Zou, Shuyuan Zhang, Sharad Malik, Jennifer Rexford, David Walker:
An assertion language for debugging SDN applications. HotSDN 2014: 91-96 - [c148]Yinlei Yu, Pramod Subramanyan, Nestan Tsiskaridze, Sharad Malik:
All-SAT Using Minimal Blocking Clauses. VLSID 2014: 86-91 - [p8]Georg Weissenbacher, Pramod Subramanyan, Sharad Malik:
Boolean Satisfiability: Solvers and Extensions. Software Systems Safety 2014: 223-278 - [i1]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. CoRR abs/1407.7468 (2014) - 2013
- [c147]Shuyuan Zhang, Sharad Malik:
SAT Based Verification of Network Data Planes. ATVA 2013: 496-505 - [c146]Yavuz Yetim, Margaret Martonosi, Sharad Malik:
Extracting useful computation from error-prone processors for streaming applications. DATE 2013: 202-207 - [c145]Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea, Sharad Malik:
Reverse engineering digital circuits using functional analysis. DATE 2013: 1277-1280 - [c144]Divjyot Sethi, Srinivas Narayana, Sharad Malik:
Abstractions for model checking SDN controllers. FMCAD 2013: 145-148 - [c143]Wenchao Li, Adrià Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia:
WordRev: Finding word-level structures in a sea of bit-level gates. HOST 2013: 67-74 - [c142]Sunha Ahn, Sharad Malik:
Modeling Firmware as Service Functions and Its Application to Test Generation. Haifa Verification Conference 2013: 61-77 - [c141]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Model Checking Unbounded Concurrent Lists. SPIN 2013: 320-340 - 2012
- [c140]Yavuz Yetim, Sharad Malik, Margaret Martonosi:
EPROF: An energy/performance/reliability optimization framework for streaming applications. ASP-DAC 2012: 769-774 - [c139]Shuyuan Zhang, Sharad Malik, Rick McGeer:
Verification of Computer Switching Networks: An Overview. ATVA 2012: 1-16 - [c138]Daniel Schwartz-Narbonne, Georg Weissenbacher, Sharad Malik:
Parallel Assertions for Architectures with Weak Memory Models. ATVA 2012: 254-268 - [c137]Daniel Schwartz-Narbonne, Feng Liu, David I. August, Sharad Malik:
passert: A Tool for Debugging Parallel Programs. CAV 2012: 751-757 - [c136]Carven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, Sharad Malik:
Specification and synthesis of hardware checkpointing and rollback mechanisms. DAC 2012: 1226-1232 - [c135]Arnab Sinha, Sharad Malik, Aarti Gupta:
Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. FMCAD 2012: 6-15 - [c134]Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation. Haifa Verification Conference 2012: 132-147 - [c133]Shuyuan Zhang, Abdulrahman Mahmoud, Sharad Malik, Sanjai Narain:
Verification and synthesis of firewalls using SAT and QBF. ICNP 2012: 1-6 - [c132]Divjyot Sethi, Muralidhar Talupur, Daniel Schwartz-Narbonne, Sharad Malik:
Parameterized Model Checking of Fine Grained Concurrency. SPIN 2012: 208-226 - [c131]Georg Weissenbacher, Daniel Kroening, Sharad Malik:
Wolverine: Battling Bugs with Interpolants - (Competition Contribution). TACAS 2012: 556-558 - [p7]Georg Weissenbacher, Sharad Malik:
Boolean Satisfiability Solvers: Techniques and Extensions. Software Safety and Security 2012: 205-253 - 2011
- [j52]Divjyot Sethi, Yogesh S. Mahajan, Sharad Malik:
Specification and encoding of transaction interaction properties. Formal Methods Syst. Des. 39(2): 144-164 (2011) - [c130]Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Post-silicon fault localisation using maximum satisfiability and backbones. FMCAD 2011: 63-66 - [c129]Charlie Shucheng Zhu, Georg Weissenbacher, Divjyot Sethi, Sharad Malik:
SAT-based techniques for determining backbones for post-silicon fault localisation. HLDVT 2011: 84-91 - [c128]Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta:
Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. Haifa Verification Conference 2011: 95-114 - [c127]Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta:
Predictive analysis for detecting serializability violations through Trace Segmentation. MEMOCODE 2011: 99-108 - [c126]Daniel Schwartz-Narbonne, Feng Liu, Tarun Pondicherry, David I. August, Sharad Malik:
Parallel assertions for debugging parallel programs. MEMOCODE 2011: 181-190 - [c125]Sharad Malik:
Runtime Verification: A Computer Architecture Perspective. RV 2011: 49-62 - [c124]Sanjai Narain, Sharad Malik, Ehab Al-Shaer:
Towards Eliminating Configuration Errors in Cyber Infrastructure. SafeConfig 2011 - 2010
- [c123]Yogesh S. Mahajan, Sharad Malik:
Utility of transaction-level hardware models in refinement checking. HLDVT 2010: 121-128 - [c122]Arnab Sinha, Sharad Malik:
Runtime checking of serializability in software transactional memory. IPDPS 2010: 1-12
2000 – 2009
- 2009
- [j51]Sharad Malik, Lintao Zhang:
Boolean satisfiability from theoretical hardness to practical success. Commun. ACM 52(8): 76-82 (2009) - [j50]Aarti Gupta, Sharad Malik:
Preface. Formal Methods Syst. Des. 35(1): 1 (2009) - [c121]Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik:
Supporting RTL flow compatibility in a microarchitecture-level design framework. CODES+ISSS 2009: 343-352 - [p6]João Marques-Silva, Inês Lynce, Sharad Malik:
Conflict-Driven Clause Learning SAT Solvers. Handbook of Satisfiability 2009: 131-153 - 2008
- [j49]Jan M. Rabaey, Sharad Malik:
Challenges and Solutions for Late- and Post-Silicon Design. IEEE Des. Test Comput. 25(4): 296-302 (2008) - [j48]Sanjai Narain, Gary Levin, Sharad Malik, Vikram Kaul:
Declarative Infrastructure Configuration Synthesis and Debugging. J. Netw. Syst. Manag. 16(3): 235-258 (2008) - [c120]Kaiyu Chen, Sharad Malik, Priyadarsan Patra:
Runtime validation of memory ordering using constraint graph checking. HPCA 2008: 415-426 - [c119]Kaiyu Chen, Sharad Malik, Priyadarsan Patra:
Runtime Validation of Transactional Memory Systems. ISQED 2008: 750-756 - [c118]Sharad Malik:
Hardware Verification: Techniques, Methodology and Solutions. TACAS 2008: 1 - [c117]Yinlei Yu, Cameron Brien, Sharad Malik:
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. VLSI Design 2008: 461-468 - [e2]Aarti Gupta, Sharad Malik:
Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings. Lecture Notes in Computer Science 5123, Springer 2008, ISBN 978-3-540-70543-7 [contents] - 2007
- [j47]Xinping Zhu, Sharad Malik:
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. ACM Trans. Design Autom. Electr. Syst. 12(1): 6:1-6:24 (2007) - [c116]Yogesh S. Mahajan, Sharad Malik:
Automating Hazard Checking in Transaction-Level Microarchitecture Models. FMCAD 2007: 62-65 - [c115]Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin:
Verification Driven Formal Architecture and Microarchitecture Modeling. MEMOCODE 2007: 123-132 - [c114]Zhaohui Fu, Sharad Malik:
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. VLSI Design 2007: 37-42 - [p5]Wei Qin, Sharad Malik:
Architecture Description Languages for Retargetable Compilation. The Compiler Design Handbook, 2nd ed. 2007: 16 - [p4]Subramanian Rajagopalan, Sharad Malik:
A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook, 2nd ed. 2007: 18 - 2006
- [j46]Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, Sharad Malik, David I. August:
The Liberty Simulation Environment: A deliberate approach to high-level system modeling. ACM Trans. Comput. Syst. 24(3): 211-249 (2006) - [j45]Xinping Zhu, Wei Qin, Sharad Malik:
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 707-716 (2006) - [c113]Cameron Brien, Sharad Malik:
Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. FMCAD 2006: 49-50 - [c112]Zhaohui Fu, Sharad Malik:
Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. ICCAD 2006: 852-859 - [c111]Kaiyu Chen, Sharad Malik:
Dependable Multithreaded Processing Using Runtime Validation. PRDC 2006: 275-286 - [c110]Yinlei Yu, Sharad Malik:
Lemma Learning in SMT on Linear Constraints. SAT 2006: 142-155 - [c109]Zhaohui Fu, Sharad Malik:
On Solving the Partial MAX-SAT Problem. SAT 2006: 252-265 - [c108]Daijue Tang, Sharad Malik:
Solving Quantified Boolean Formulas with Circuit Observability Don't Cares. SAT 2006: 368-381 - 2005
- [j44]David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai, Manish Vachharajani, Paul Willmann:
Achieving Structural and Composable Modeling of Complex Systems. Int. J. Parallel Program. 33(2-3): 81-101 (2005) - [c107]Yinlei Yu, Sharad Malik:
Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. ASP-DAC 2005: 1047-1051 - [c106]Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip:
Symmetry Reduction in SAT-Based Model Checking. CAV 2005: 125-138 - [c105]Fen Xie, Margaret Martonosi, Sharad Malik:
Efficient behavior-driven runtime dynamic voltage scaling policies. CODES+ISSS 2005: 105-110 - [c104]Zhaohui Fu, Yinlei Yu, Sharad Malik:
Considering Circuit Observability Don't Cares in CNF Satisfiability. DATE 2005: 1108-1113 - [c103]Hangsheng Wang, Li-Shiuan Peh, Sharad Malik:
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. DATE 2005: 1238-1243 - [c102]Sharad Malik:
A Case for Runtime Validation of Hardware. Haifa Verification Conference 2005: 30-42 - [c101]Ali Alphan Bayazit, Sharad Malik:
Complementary use of runtime validation and model checking. ICCAD 2005: 1052-1059 - [c100]Fen Xie, Margaret Martonosi, Sharad Malik:
Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. ISLPED 2005: 287-292 - [c99]Wei Qin, Sharad Malik:
A Study of Architecture Description Languages from a Model-based Perspective. MTV 2005: 3-11 - 2004
- [j43]Carl Pixley, Sharad Malik:
Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Des. Test Comput. 21(6): 461-463 (2004) - [j42]Fen Xie, Margaret Martonosi, Sharad Malik:
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. ACM Trans. Archit. Code Optim. 1(3): 323-367 (2004) - [j41]Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo:
The design of dynamically reconfigurable datapath coprocessors. ACM Trans. Embed. Comput. Syst. 3(2): 361-384 (2004) - [c98]Xinping Zhu, Wei Qin, Sharad Malik:
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. CODES+ISSS 2004: 66-71 - [c97]Manish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August:
Facilitating reuse in hardware models with enhanced type inference. CODES+ISSS 2004: 86-91 - [c96]Xinping Zhu, Sharad Malik:
Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. DATE 2004: 1244-1249 - [c95]David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai:
Achieving Structural and Composable Modeling of Complex Systems. IPDPS Next Generation Software Program - NSFNGS - PI Workshop 2004 - [c94]Wei Qin, Subramanian Rajagopalan, Sharad Malik:
A formal concurrency model based architecture description language for synthesis of software development tools. LCTES 2004: 47-56 - [c93]Yogesh S. Mahajan, Zhaohui Fu, Sharad Malik:
Zchaff2004: An Efficient SAT Solver. SAT (Selected Papers 2004: 360-375 - [c92]Darsh Ranjan, Daijue Tang, Sharad Malik:
A Comparative Study of 2QBF Algorithms. SAT 2004 - [c91]Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik:
Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. SAT 2004 - [c90]Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik:
Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. SAT (Selected Papers 2004: 292-305 - [e1]Sharad Malik, Limor Fix, Andrew B. Kahng:
Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004. ACM 2004, ISBN 1-58113-828-8 [contents] - 2003
- [j40]Hangsheng Wang, Li-Shiuan Peh, Sharad Malik:
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. IEEE Micro 23(1): 26-35 (2003) - [c89]Shaojie Wang, Sharad Malik:
Synthesizing operating system based device drivers in embedded systems. CODES+ISSS 2003: 37-44 - [c88]Wei Qin, Sharad Malik:
Automated synthesis of efficient binary decoders for retargetable software toolkits. DAC 2003: 764-769 - [c87]Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi:
Modeling and Integration of Peripheral Devices in Embedded Systems. DATE 2003: 10136-10141 - [c86]Wei Qin, Sharad Malik:
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. DATE 2003: 10556-10561 - [c85]Lintao Zhang, Sharad Malik:
Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. DATE 2003: 10880-10885 - [c84]Hangsheng Wang, Li-Shiuan Peh, Sharad Malik:
Power-driven Design of Router Microarchitectures in On-chip Networks. MICRO 2003: 105-116 - [c83]Fen Xie, Margaret Martonosi, Sharad Malik:
Compile-time dynamic voltage scaling settings: opportunities and limits. PLDI 2003: 49-62 - [c82]Lintao Zhang, Sharad Malik:
Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms. SAT 2003: 287-298 - [p3]Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi:
Modeling and Integration of Peripheral Devices in Embedded Systems. Embedded Software for SoC 2003: 69-82 - 2002
- [j39]Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik:
Developing Architectural Platforms: A Disciplined Approach. IEEE Des. Test Comput. 19(6): 6-16 (2002) - [j38]Janett Mohnke, Paul Molitor, Sharad Malik:
Limits of Using Signatures for Permutation Independent Boolean Comparison. Formal Methods Syst. Des. 21(2): 167-191 (2002) - [c81]Lintao Zhang, Sharad Malik:
The Quest for Efficient Boolean Satisfiability Solvers. CADE 2002: 295-313 - [c80]Lintao Zhang, Sharad Malik:
The Quest for Efficient Boolean Satisfiability Solvers. CAV 2002: 17-36 - [c79]Lintao Zhang, Sharad Malik:
Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation. CP 2002: 200-215 - [c78]Zhining Huang, Sharad Malik:
Exploiting operation level parallelism through dynamically reconfigurable datapaths. DAC 2002: 337-342 - [c77]Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey:
Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? DAC 2002: 479 - [c76]Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik:
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750 - [c75]Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh:
Design Tools for Application Specific Embedded Processors. EMSOFT 2002: 319-333 - [c74]Hangsheng Wang, Li-Shiuan Peh, Sharad Malik:
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. Hot Interconnects 2002: 21-27 - [c73]Lintao Zhang, Sharad Malik:
Conflict driven learning in a quantified Boolean Satisfiability solver. ICCAD 2002: 442-449 - [c72]Xinping Zhu, Sharad Malik:
A hierarchical modeling framework for on-chip communication architectures. ICCAD 2002: 663-671 - [c71]Kurt Keutzer, Sharad Malik, A. Richard Newton:
From ASIC to ASIP: The Next Design Discontinuity. ICCD 2002: 84-90 - [c70]Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano:
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. ISSS 2002: 38-43 - [c69]Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik:
Orion: a power-performance simulator for interconnection networks. MICRO 2002: 294-305 - [p2]Wei Qin, Sharad Malik:
Architecture Description Languages for Retargetable Compilation. The Compiler Design Handbook 2002: 535-564 - [p1]Subramanian Rajagopalan, Sharad Malik:
Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook 2002: 603-630 - 2001
- [j37]Janett Mohnke, Paul Molitor, Sharad Malik:
Application of BDDs in Boolean matching techniques for formal logic combinational verification. Int. J. Softw. Tools Technol. Transf. 3(2): 207-216 (2001) - [j36]Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1319-1328 (2001) - [j35]Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. 6(4): 569-590 (2001) - [c68]Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik:
Optimal Live Range Merge for Address Register Allocation in Embedded Programs. CC 2001: 274-288 - [c67]Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik:
Chaff: Engineering an Efficient SAT Solver. DAC 2001: 530-535 - [c66]Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. DAC 2001: 667-672 - [c65]Zhining Huang, Sharad Malik:
Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. DATE 2001: 735 - [c64]Sharad Malik:
Embedded Software Implementation Tools for Fully Programmable Application Specific Systems. EMSOFT 2001: 254-256 - [c63]Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik:
Efficient Conflict Driven Learning in Boolean Satisfiability Solver. ICCAD 2001: 279-285 - [c62]Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik:
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD 2001: 286-292 - [c61]Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan:
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. ICCD 2001: 447-452 - [c60]Kaiyu Chen, Sharad Malik, David I. August:
Retargetable static timing analysis for embedded software. ISSS 2001: 39-44 - [c59]Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan:
Accelerating boolean satisfiability through application specific processing. ISSS 2001: 244-249 - 2000
- [j34]Ashok Sudarsanam, Sharad Malik:
Simultaneous reference allocation in code generation for dual data memory bank ASIPs. ACM Trans. Design Autom. Electr. Syst. 5(2): 242-264 (2000) - [j33]Ying Zhao, Sharad Malik:
Exact memory size estimation for array computations. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 517-521 (2000) - [c58]Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik:
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. CASES 2000: 157-164 - [c57]Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne H. Wolf:
Embedded systems education (panel abstract). DAC 2000: 519 - [c56]Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh:
Incremental CAD. ICCAD 2000: 236-243 - [c55]Somnath Ghosh, Margaret Martonosi, Sharad Malik:
Automated cache optimizations using CME driven diagnosis. ICS 2000: 316-326 - [c54]T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik:
Processor Evaluation in an Embedded Systems Design Environment. VLSI Design 2000: 98-103
1990 – 1999
- 1999
- [b1]Yau-Tsun Steven Li, Sharad Malik:
Performance analysis of real-time embedded software. Springer 1999, ISBN 978-0-7923-8382-6, pp. I-XVI, 1-146 - [j32]Ashok Sudarsanam, Sharad Malik, Steven W. K. Tjiang, Stan Y. Liao:
Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis. Des. Autom. Embed. Syst. 4(1): 41-59 (1999) - [j31]Ashok Sudarsanam, Sharad Malik, Masahiro Fujita:
A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. Des. Autom. Embed. Syst. 4(2-3): 187-206 (1999) - [j30]Janett Mohnke, Paul Molitor, Sharad Malik:
Establishing latch correspondence for sequential circuits using distinguishing signatures. Integr. 27(1): 33-46 (1999) - [j29]Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 861-868 (1999) - [j28]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Performance estimation of embedded software with instruction cache modeling. ACM Trans. Design Autom. Electr. Syst. 4(3): 257-279 (1999) - [j27]Somnath Ghosh, Margaret Martonosi, Sharad Malik:
Cache miss equations: a compiler framework for analyzing and tuning memory behavior. ACM Trans. Program. Lang. Syst. 21(4): 703-746 (1999) - [c53]Aarti Gupta, Pranav Ashar, Sharad Malik:
Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME 1999: 350-353 - [c52]Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik:
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES 1999: 2-6 - [c51]Ying Zhao, Sharad Malik:
Exact Memory Size Estimation for Array Computations without Loop Unrolling. DAC 1999: 811-816 - [c50]Srinivas Devadas, Sharad Malik, José Monteiro, Luciano Lavagno:
CAD Techniques for Embedded System Design. VLSI Design 1999: 608 - 1998
- [j26]Vivek Tiwari, Sharad Malik, Pranav Ashar:
Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1051-1060 (1998) - [j25]Guido Araujo, Sharad Malik:
Code generation for fixed-point DSPs. ACM Trans. Design Autom. Electr. Syst. 3(2): 136-161 (1998) - [c49]Somnath Ghosh, Margaret Martonosi, Sharad Malik:
Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity. ASPLOS 1998: 228-239 - [c48]Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi:
Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. DAC 1998: 194-199 - [c47]Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
Accelerating Boolean Satisfiability with Configurable Hardware. FCCM 1998: 186-195 - [c46]Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
Solving Boolean Satisfiability with Dynamic Hardware Configurations. FPL 1998: 326-335 - 1997
- [j24]Noriya Kobayashi, Sharad Malik:
Delay abstraction in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1205-1212 (1997) - [j23]Yau-Tsun Steven Li, Sharad Malik:
Performance analysis of embedded software using implicit path enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12): 1477-1487 (1997) - [j22]Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 123-135 (1997) - [c45]Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li:
Static Timing Analysis of Embedded Software. DAC 1997: 147-152 - [c44]Aarti Gupta, Sharad Malik, Pranav Ashar:
Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC 1997: 740-745 - [c43]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software. Euro-Par 1997: 1308-1315 - [c42]Ashok Sudarsanam, Sharad Malik, Steven W. K. Tjiang, Stan Y. Liao:
Optimization of embedded DSP programs using post-pass data-flow analysis. ICASSP 1997: 695-698 - [c41]Somnath Ghosh, Margaret Martonosi, Sharad Malik:
Cache Miss Equations: An Analytical Representation of Cache Misses. International Conference on Supercomputing 1997: 317-324 - [c40]Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez:
Dynamic Power Management for Microprocessors: A Case Study. VLSI Design 1997: 185-192 - 1996
- [j21]Vivek Tiwari, Pranav Ashar, Sharad Malik:
Technology mapping for low power in logic synthesis. Integr. 20(3): 243-268 (1996) - [j20]Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee:
Instruction level power analysis and optimization of software. J. VLSI Signal Process. 13(2-3): 223-238 (1996) - [c39]Guido Araujo, Sharad Malik, Mike Tien-Chien Lee:
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. DAC 1996: 591-596 - [c38]Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. ICCAD 1996: 346-353 - [c37]Vigyan Singhal, Sharad Malik, Robert K. Brayton:
The case for retiming with explicit reset circuitry. ICCAD 1996: 618-625 - [c36]Guido Araujo, Ashok Sudarsanam, Sharad Malik:
Instruction Set Design and Optimizations for Address Computation in DSP Architectures. ISSS 1996: 102-107 - [c35]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Cache modeling for real-time software: beyond direct mapped instruction caches. RTSS 1996: 254-263 - [c34]Kurt Keutzer, Sharad Malik:
Register Transfer Level Synthesis: From Theory to Practice. VLSI Design 1996: 2 - [c33]Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee:
Instruction Level Power Analysis and Optimization of Software. VLSI Design 1996: 326-328 - 1995
- [j19]N. Nandhakumar, Sharad Malik:
Multisensor Integration for Underwater Scene Classification. Appl. Intell. 5(3): 207-216 (1995) - [j18]Pranav Ashar, Sharad Malik:
Functional timing analysis using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 1025-1030 (1995) - [j17]Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1067-1075 (1995) - [j16]Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1408-1414 (1995) - [c32]Noriya Kobayashi, Sharad Malik:
Delay abstraction in combinational logic circuits. ASP-DAC 1995 - [c31]Janett Mohnke, Paul Molitor, Sharad Malik:
Limits of using signatures for permutation independent Boolean comparison. ASP-DAC 1995 - [c30]Srinivas Devadas, Sharad Malik:
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. DAC 1995: 242-247 - [c29]Yau-Tsun Steven Li, Sharad Malik:
Performance Analysis of Embedded Software Using Implicit Path Enumeration. DAC 1995: 456-461 - [c28]Horng-Fei Jyu, Sharad Malik:
Prediction of interconnect delay in logic synthesis. ED&TC 1995: 411-417 - [c27]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Performance estimation of embedded software with instruction cache modeling. ICCAD 1995: 380-387 - [c26]Ashok Sudarsanam, Sharad Malik:
Memory bank and register allocation in software synthesis for ASIPs. ICCAD 1995: 388-392 - [c25]Pranav Ashar, Sharad Malik:
Fast functional simulation using branching programs. ICCAD 1995: 408-412 - [c24]Vivek Tiwari, Sharad Malik, Pranav Ashar:
Guarded evaluation: pushing power management to logic synthesis/design. ISLPD 1995: 221-226 - [c23]Guido Araujo, Sharad Malik:
Optimal code generation for embedded memory non-homogeneous register architectures. ISSS 1995: 36-41 - [c22]Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
Power analysis and low-power scheduling techniques for embedded DSP software. ISSS 1995: 110-115 - [c21]Yau-Tsun Steven Li, Sharad Malik:
Performance Analysis of Embedded Software Using Implicit Path Enumeration. Workshop on Languages, Compilers, & Tools for Real-Time Systems 1995: 88-98 - [c20]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. RTSS 1995: 298-307 - [c19]Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. VLSI Design 1995: 104-109 - 1994
- [j15]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 814-822 (1994) - [j14]Sharad Malik:
Analysis of cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 950-956 (1994) - [j13]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Certified timing verification and the transition delay of a logic circuit. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 333-342 (1994) - [j12]Vivek Tiwari, Sharad Malik, Andrew Wolfe:
Power analysis of embedded software: a first step towards software power minimization. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 437-445 (1994) - [j11]Teresa H. Meng, Sharad Malik:
Editorial. J. VLSI Signal Process. 7(1-2): 5-6 (1994) - [j10]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Verification of asynchronous interface circuits with bounded wire delays. J. VLSI Signal Process. 7(1-2): 161-182 (1994) - [c18]Pranav Ashar, Sharad Malik:
Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. DAC 1994: 77-80 - [c17]Horng-Fei Jyu, Sharad Malik:
Statistical Delay Modeling in Logic Design and Synthesis. DAC 1994: 126-130 - [c16]Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang:
Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64 - [c15]Vivek Tiwari, Sharad Malik, Andrew Wolfe:
Power analysis of embedded software: a first step towards software power minimization. ICCAD 1994: 384-390 - 1993
- [j9]Srinivas Devadas, Kurt Keutzer, Sharad Malik:
A synthesis-based test generation and compaction algorithm for multifaults. J. Electron. Test. 4(1): 91-104 (1993) - [j8]Janett Mohnke, Sharad Malik:
Permutation and phase independent Boolean comparison. Integr. 16(2): 109-129 (1993) - [j7]Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 568-578 (1993) - [j6]Srinivas Devadas, Kurt Keutzer, Sharad Malik:
Computation of floating mode delay in combinational circuits: theory and algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1913-1923 (1993) - [j5]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1924-1936 (1993) - [j4]Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer:
Statistical timing analysis of combinational logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 1(2): 126-137 (1993) - [c14]Vivek Tiwari, Pranav Ashar, Sharad Malik:
Technology Mapping for Lower Power. DAC 1993: 74-79 - [c13]Sharad Malik:
Analysis of cyclic combinational circuits. ICCAD 1993: 618-625 - [c12]Horng-Fei Jyu, Sharad Malik:
Statistical Timing Optimization of Combinatorial Logic Circuits. ICCD 1993: 77-80 - 1992
- [j3]Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Symbolic minimization of multilevel logic and the input encoding problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 825-843 (1992) - [c11]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC 1992: 549-555 - [c10]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Verification of asynchronous interface circuits with bounded wire delays. ICCAD 1992: 188-195 - [c9]Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD 1992: 510-517 - [c8]Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik:
Statistical Timing Analysis of Combinational Circuits. ICCD 1992: 38-43 - 1991
- [j2]Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 74-84 (1991) - [j1]Kurt Keutzer, Sharad Malik, Alexander Saldanha:
Is redundancy necessary to reduce delay? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 427-435 (1991) - [c7]Srinivas Devadas, Kurt Keutzer, Sharad Malik:
A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. DAC 1991: 359-365 - [c6]Srinivas Devadas, Kurt Keutzer, Sharad Malik:
Delay Computation in Combinational Logic Circuits: Theory and Algorithms. ICCAD 1991: 176-179 - 1990
- [c5]Kurt Keutzer, Sharad Malik, Alexander Saldanha:
Is Redundancy Necessary to Reduce Delay. DAC 1990: 228-234 - [c4]Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton:
Algorithms for Discrete Function Manipulation. ICCAD 1990: 92-95 - [c3]Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Optimization of Pipelined Circuits. ICCAD 1990: 410-413 - [c2]Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. ICCAD 1990: 560-563
1980 – 1989
- 1988
- [c1]Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD 1988: 6-9
Coauthor Index
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