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ORCIDOndrej Novák
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2020 – today
- 2023
[j9]Ondrej Novák
:
Nonlinear compression block codes: Exact and random search strategy. Microprocess. Microsystems 101: 104877 (2023)- [c41]Ondrej Novák:
Deterministic Search Strategy of Compression Codes. DSD 2023: 198-205 - 2022
- [c40]Ondrej Novák:
Nonlinear Compression Block Codes Search Strategy. DSD 2022: 665-670 - 2021
- [c39]Ondrej Novák:
Search Strategy of Large Nonlinear Block Codes. DSD 2021: 527-534 - 2020
- [j8]Ondrej Novák, Martin Rozkovec, Jan Plíva:
Decompressors using nonlinear codes. Microprocess. Microsystems 76: 103076 (2020)
2010 – 2019
- 2019
- [c38]Ondrej Novák, Kamila K. Konopinska, Mark E. Meyerhoff, Richard B. Brown:
Portable Bluetooth Microsystem for Electrochemically Modulated Nitric Oxide-Releasing Catheters. BioCAS 2019: 1-4 - [c37]Ondrej Novák:
Nonlinear Compression Codes Used In IC Testing. DDECS 2019: 1-4 - [c36]Ondrej Novák, Martin Rozkovec, Jan Plíva:
Combinational Decompressors with Nonlinear Codes. DSD 2019: 500-505 - [c35]Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková:
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC 2019: 1-4 - 2018
- [j7]Ondrej Novák, Zdenek Plíva:
Test response compaction method with improved detection and diagnostic abilities. Microelectron. Reliab. 80: 249-256 (2018) - [j6]Zoran Stamenkovic, Ondrej Novák, Witold A. Pleskacz:
Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017). Microelectron. Reliab. 81: 287 (2018) - [c34]Ondrej Novák:
Test Compression Using Extended Nonlinear Binary Codes. IOLTS 2018: 255-256 - 2017
- [j5]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Sequential Test Decompressors with Fast Tester Bits Wide-Spreading. J. Circuits Syst. Comput. 26(8): 1740001:1-1740001:16 (2017) - [c33]Ondrej Novák, Zdenek Plíva:
Logic testing with test-per-clock pattern loading and improved diagnostic abilities. DDECS 2017: 54-59 - [c32]Ondrej Novák:
Extended binary nonlinear codes and their application in testing and compression. ETS 2017: 1-2 - [e2]Manfred Dietrich, Ondrej Novák:
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017. IEEE 2017, ISBN 978-1-5386-0472-4 [contents] - 2016
- [c31]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Sequential test decompressors with fast variable wide spreading. DDECS 2016: 132-137 - [c30]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test Decompressor Effectivity Improvement. DSD 2016: 661-664 - [c29]Ondrej Novák, Richard B. Brown:
An empirical model of UWB large-scale signal fading in neocortical research. ISCAS 2016: 2439-2442 - 2015
- [j4]Markéta Tomková, Jakub Tomek, Ondrej Novák, Ondrej Zelenka, Josef Syka, Cyril Brom:
Formation and disruption of tonotopy in a large-scale model of the auditory cortex. J. Comput. Neurosci. 39(2): 131-153 (2015) - [c28]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs. DDECS 2015: 9-14 - [c27]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test compression for circuits with multiple scan chains. LATS 2015: 1-6 - 2014
- [c26]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test-data compression with low number of channels and short test time. DDECS 2014: 104-109 - [c25]Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák:
A highly flexible reconfigurable system on a Xilinx FPGA. ReConFig 2014: 1-6 - 2013
- [c24]Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák:
Relocation of reconfigurable modules on Xilinx FPGA. DDECS 2013: 175-180 - [c23]Martin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec:
Test pattern decompression in parallel scan chain architecture. DDECS 2013: 219-223 - 2012
- [c22]Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
An evaluation of the application dependent FPGA test method. DDECS 2012: 22-25 - [c21]Martin Chloupek, Ondrej Novák, Jiri Jenícek:
On test time reduction using pattern overlapping, broadcasting and on-chip decompression. DDECS 2012: 300-305 - 2011
- [c20]Jiri Jenícek, Martin Rozkovec, Ondrej Novák:
Test vector overlapping based compression tool for narrow test access mechanism. DDECS 2011: 387-392 - [c19]Jiri Jenícek, Ondrej Novák, Martin Chloupek:
Advanced scan chain configuration method for broadcast decompressor architecture. EWDTS 2011: 140-143 - [c18]Martin Chloupek, Ondrej Novák:
Scan chain configuration method for broadcast decompressor architecture. LATW 2011: 1-5 - 2010
- [c17]Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
Application Dependent FPGA Testing Method. DSD 2010: 525-530 - [c16]Jan Balach, Ondrej Novák:
Reconfigurable Fault-Tolerant System Sychronization. DSD 2010: 817-820 - [c15]Jiri Jenícek, Ondrej Novák:
COMPAS - Advanced test compressor. EWDTS 2010: 543-548 - [c14]Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
Application dependent FPGA testing method using compressed deterministic test vectors. IOLTS 2010: 192-193
2000 – 2009
- 2009
- [c13]Martin Rozkovec, Ondrej Novák:
Structural test of programmed FPGA circuits. DDECS 2009: 136-139 - 2007
- [c12]Jiri Jenícek, Ondrej Novák:
Test Pattern Compression Based on Pattern Overlapping. DDECS 2007: 29-34 - [c11]Leos Kafka, Martin Danek, Ondrej Novák:
A Novel Emulation Technique that Preserves Circuit Structure and Timing. SoC 2007: 1-4 - 2006
- [j3]Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar:
Conference Reports. IEEE Des. Test Comput. 23(4): 262-265 (2006) - [c10]Martin Stáva, Ondrej Novák:
HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. DDECS 2006: 250-252 - [c9]Leos Kafka, Ondrej Novák:
FPGA-based Fault Simulator. DDECS 2006: 274-278 - [c8]Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský:
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. DFT 2006: 300-308 - [c7]Martin Stáva, Ondrej Novák:
Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. DSD 2006: 251-256 - [e1]Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek:
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, ISBN 1-4244-0185-2 [contents] - 2005
- [c6]Ondrej Novák, Jirí Zahrádka, Zdenek Plíva:
COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits. EDCC 2005: 403-414 - 2004
- [j2]Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa:
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electron. Test. 20(1): 109-122 (2004) - 2003
- [c5]Ondrej Novák:
Comparison of Test Pattern Decompression Techniques. DATE 2003: 11182-11183 - 2001
- [c4]Ondrej Novák, Jiri Nosek:
Test Pattern Decompression Using a Scan Chain. DFT 2001: 110-115 - [c3]Ondrej Novák, Jiri Nosek:
Test-per-Clock Testing of the Circuits with Scan. IOLTW 2001: 90- - 2000
- [c2]Ondrej Novák, Jiri Nosek:
On Using Deterministic Test Sets in BIST. IOLTW 2000: 127-132
1990 – 1999
- 1999
- [c1]Ondrej Novák:
Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata. EDCC 1999: 303-320
1980 – 1989
- 1988
- [j1]P. Golan, Ondrej Novák, Jan Hlavicka:
Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. IEEE Trans. Computers 37(4): 496-500 (1988)
Coauthor Index
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