45. DAC 2008: Anaheim, CA, USA

iDesign I

Special session: enabling concurrency in EDA

CAD for FPGA

Analog performance modeling and synthesis

Novel techniques in embedded processor design

Panel

Special session: student design contest

Panel

Panel

Formal verification technology

Layout techniques for modern chip designs

Application mapping and power efficiency

Variation-aware design

iDesign II

Multi-core simulation, mixed-signal power optimization and nanodevices

Experiences and advances in formal and dynamic verification

Emerging nano/biotechnologies

Cache optimization and embedded systems modeling

Panel

Analytical modeling and simulation of complex processing systems

Special session: wild and crazy ideas

Panel

Diagnosis and debug

Architectural and precision optimization in high-level synthesis

Extraction, interconnect and timing

Architectures for on-chip communication

Special session: CMOS gate modeling for timing, noise, and power: rapidly changing paradigm

Advanced wireless design

Manufacturing aware design and design aware manufacturing

Advances in sequential optimization

Panel

Beyond the die - packaging and die stacking

Special session: ESL methodologies for platform-based synthesis

Special session: wireless: business meets technology

Leakage analysis and optimization

Design methods for on-chip communication

Panel

New advances in logic synthesis

Special session: 3-D semiconductor integration & packaging

Statistical timing analysis

Performance driven layout optimization