• 
  Limor Fix (Ed.): Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008. ACM 2008 ISBN 978-1-60558-115-6

iDesign I

• 
  Steve Golson, Pete Churchill: Flow engineering for physical implementation: theory and practice. 1

Special session: enabling concurrency in EDA

• 
  Michael Garland: Sparse matrix computations on manycore GPU's. 2-6
• 
  Tim Mattson, Michael Wrinn: Parallel programming: can we PLEASE get it right this time? 7-11
• 
  Bryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su: Parallelizing CAD: a timely research agenda for EDA. 12-17

CAD for FPGA

• 
  Tomasz S. Czajkowski, Stephen Dean Brown: Functionally linear decomposition and synthesis of logic circuits for FPGAs. 18-23
• 
  Yu Hu, Victor Shih, Rupak Majumdar, Lei He: FPGA area reduction by multi-output function based sequential resynthesis. 24-29
• 
  Tien-Yuan Hsu, Ting-Chi Wang: A generalized network flow based algorithm for power-aware FPGA memory mapping. 30-33
• 
  Kenneth Eguro, Scott Hauck: Enhancing timing-driven FPGA placement for pipelined netlists. 34-37

Analog performance modeling and synthesis

• 
  Xin Li, Hongzhou Liu: Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations. 38-43
• 
  Angan Das, Ranga Vemuri: Topology synthesis of analog circuits based on adaptively generated building blocks. 44-49
• 
  Mark Po-Hung Lin, Shyh-Chang Lin: Analog placement based on hierarchical module clustering. 50-55

Novel techniques in embedded processor design

• 
  Lars Bauer, Muhammad Shafique, Jörg Henkel: Run-time instruction set selection in a transmutable embedded processor. 56-61
• 
  Yee Jern Chong, Sri Parameswaran: Rapid application specific floating-point unit generation with bit-alignment. 62-67
• 
  Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum: Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. 68-71
• 
  Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski: C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). 72-75

Panel

• 
  Tiffany Sparks, Pete Weitzner, Luc Burgun, Russell Lefevre, Todd Cutler, Clayton Parker, Vicki Hadfield, Chris Rowen: Election year: what the electronics industry needs---and can expect---from the incoming administration. 76-77

Special session: student design contest

• 
  Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang: A 242mW, 10mm²1080p H.264/AVC high profile encoder chip. 78-83
• 
  Taeg Sang Cho, Kyeong-jae Lee, Jing Kong, Anantha P. Chandrakasan: The design of a low power carbon nanotube chemical sensor system. 84-89
• 
  Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen: iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor. 90-95
• 
  Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo: Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor. 96-101
• 
  Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips: A MIPS R2000 implementation. 102-107
• 
  Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy: Process variation tolerant SRAM array for ultra low voltage applications. 108-113
• 
  Yuen-Hui Chee, Mike Koplow, Michael Mark, Nathan Pletcher, Mike Seeman, Fred Burghardt, Dan Steingart, Jan M. Rabaey, Paul K. Wright, Seth Sanders: PicoCube: a 1 cm³ sensor node powered by harvested energy. 114-119
• 
  Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger: An 8x8 run-time reconfigurable FPGA embedded in a SoC. 120-125

Panel

• 
  Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou: Reinventing EDA with manycore processors. 126-127

Panel

• 
  Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne Wolf, Achim Nohl, Drew Wingard, Mike Muller: Multicore design is the challenge! what is the solution? 128-130

Formal verification technology

• 
  In-Ho Moon: Compositional verification of retiming and sequential optimizations. 131-136
• 
  Malay K. Ganai, Aarti Gupta: Tunneling and slicing: towards scalable BMC. 137-142
• 
  Yan Chen, Fei Xie, Jin Yang: Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. 143-148
• 
  Paul T. Darga, Karem A. Sakallah, Igor L. Markov: Faster symmetry discovery using sparsity of symmetries. 149-154

Layout techniques for modern chip designs

• 
  Dipanjan Sengupta, Resve A. Saleh: Application-driven floorplan-aware voltage island design. 155-160
• 
  Jackey Z. Yan, Chris Chu: DeFer: deferred decision making enabled fixed-outline floorplanner. 161-166
• 
  Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang: Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. 167-172
• 
  Tao Xu, Krishnendu Chakrabarty: Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips. 173-178

Application mapping and power efficiency

• 
  Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar: Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. 179-184
• 
  Ranjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra: Feedback-controlled reliability-aware power management for real-time embedded systems. 185-190
• 
  Michel Goraczko, Jie Liu, Dimitrios Lymberopoulos, Slobodan Matic, Bodhi Priyantha, Feng Zhao: Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems. 191-196
• 
  Ya-shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao: Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. 197-200
• 
  Rogier Baert, Eddy de Greef, Erik Brockmeyer: An automatic scratch pad memory management tool and MPEG-4 encoder case study. 201-204

Variation-aware design

• 
  Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis: A methodology for statistical estimation of read access yield in SRAMs. 205-210
• 
  Jieyi Long, Seda Ogrenci Memik: Automated design of self-adjusting pipelines. 211-216
• 
  Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout: Speedpath prediction based on learning from a small set of examples. 217-222
• 
  Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni: Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. 223-226
• 
  Amit Goel, Sarma B. K. Vrudhula: Statistical waveform and current source based standard cell models for accurate timing analysis. 227-230

iDesign II

• 
  Clifford E. Cummings: SystemVerilog implicit port enhancements accelerate system design & verification. 231-236
• 
  Kelly D. Larson: Translation of an existing VMM-based SystemVerilog testbench to OVM. 237

Multi-core simulation, mixed-signal power optimization and nanodevices

• 
  Wei Dong, Peng Li, Xiaoji Ye: WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. 238-243
• 
  Brian P. Ginsburg, Anantha P. Chandrakasan: The mixed signal optimum energy point: voltage and parallelism. 244-249
• 
  Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee: Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. 250-255

Experiences and advances in formal and dynamic verification

• 
  Babu Turumella, Mukesh Sharma: Assertion-based verification of a 32 thread SPARC^TM CMT microprocessor. 256-261
• 
  Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster: Functional test selection based on unsupervised support vector analysis. 262-267
• 
  Richard C. Ho, Michael Theobald, Martin M. Deneroff, Ron O. Dror, Joseph Gagliardo, David E. Shaw: Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic. 268-271

Emerging nano/biotechnologies

• 
  Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram: Technology exploration for graphene nanoribbon FETs. 272-277
• 
  Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy: Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. 278-283
• 
  Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. 284-289

Cache optimization and embedded systems modeling

• 
  Jürgen Schnerr, Oliver Bringmann, Alexander Viehl, Wolfgang Rosenstiel: High-performance timing simulation of embedded software. 290-295
• 
  Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang: Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. 296-299
• 
  Vivy Suhendra, Tulika Mitra: Exploring locking & partitioning for predictable shared caches on multi-cores. 300-303
• 
  Garo Bournoutian, Alex Orailoglu: Miss reduction in embedded processors through dynamic, power-friendly cache design. 304-309

Panel

• 
  Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil Dutt, Giovanni Mancini: ESL hand-off: fact or EDA fiction? 310-312

Analytical modeling and simulation of complex processing systems

• 
  Sebastian Herbert, Diana Marculescu: Characterizing chip-multiprocessor variability-tolerance. 313-318
• 
  Yun Liang, Tulika Mitra: Cache modeling in probabilistic execution time analysis. 319-324
• 
  Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Multiprocessor performance estimation using hybrid simulation. 325-330
• 
  Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya: Multithreaded simulation for synchronous dataflow graphs. 331-336

Special session: wild and crazy ideas

• 
  Jay B. Brockman, Sheng Li, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi: Design of a mask-programmable memory/multiplier array using G4-FET technology. 337-338
• 
  M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli: Programmable logic circuits based on ambipolar CNFET. 339-340
• 
  Daeik D. Kim, Choongyeun Cho, Jonghae Kim: Analog parallelism in ring-based VCOs. 341-342
• 
  Claudio Favi, Edoardo Charbon: Techniques for fully integrated intra-/inter-chip optical communication. 343-344
• 
  Min Li, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor: How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach. 345-346
• 
  Puneet Gupta, Andrew B. Kahng: Bounded-lifetime integrated circuits. 347-348
• 
  Seetharam Narasimhan, Somnath Paul, Swarup Bhunia: Collective computing based on swarm intelligence. 349-350
• 
  Miodrag Potkonjak, Farinaz Koushanfar: (Bio)-behavioral CAD. 351-352

Panel

• 
  Juan C. Rey, Andreas Kuehlmann, Jan M. Rabaey, Cormac Conroy, Ted Vucurevich, Ikuya Kawasaki, Tuna B. Tarim: Next generation wireless-multimedia devices: who is up for the challenge? 353-354

Diagnosis and debug

• 
  Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Statistical diagnosis of unmodeled systematic timing effects. 355-360
• 
  Xiaochun Yu, R. D. (Shawn) Blanton: Multiple defect diagnosis using no assumptions on failing pattern characteristics. 361-366
• 
  Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton: Precise failure localization using automated layout analysis of diagnosis candidates. 367-372
• 
  Sung-Boem Park, Subhasish Mitra: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. 373-378

Architectural and precision optimization in high-level synthesis

• 
  Bita Gorjiara, Daniel Gajski: Automatic architecture refinement techniques for customizing processing elements. 379-384
• 
  Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel: Formal datapath representation and manipulation for implementing DSP transforms. 385-390
• 
  Arash Ahmadi, Mark Zwolinski: Symbolic noise analysis approach to computational hardware optimization. 391-396
• 
  Yu Pang, Katarzyna Radecka: Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. 397-402

Extraction, interconnect and timing

• 
  Khaled R. Heloue, Farid N. Najm: Parameterized timing analysis with general delay models and arbitrary variation sources. 403-408
• 
  Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy: DeMOR: decentralized model order reduction of linear networks with massive ports. 409-414
• 
  Tarek Moselhy, Luca Daniel: Stochastic integral equation solver for efficient variation-aware interconnect extraction. 415-420
• 
  Ki Jin Han, Madhavan Swaminathan, Ege Engin: Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects. 421-424
• 
  Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta: Driver waveform computation for timing analysis with multiple voltage threshold driver models. 425-428

Architectures for on-chip communication

• 
  Hazem Moussa, Amer Baghdadi, Michel Jézéquel: Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. 429-434
• 
  Aydin O. Balkan, Gang Qu, Uzi Vishkin: An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing. 435-440
• 
  Zhen Zhang, Alain Greiner, Sami Taktak: A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. 441-446
• 
  Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo: A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. 447-452

Special session: CMOS gate modeling for timing, noise, and power: rapidly changing paradigm

• 
  Peter Feldmann, Soroush Abbaspour: Towards a more physical approach to gate modeling for timing, noise, and power. 453-455
• 
  S. Raja, F. Varadi, Murat R. Becer, Joao Geada: Transistor level gate modeling for accurate and fast timing, noise, and power analysis. 456-461
• 
  Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin: A "true" electrical cell model for timing, noise, and power grid verification. 462-467
• 
  Igor Keller, King Ho Tam, Vinod Kariat: Challenges in gate level modeling for delay and SI at 65nm and below. 468-473
• 
  Richard Trihy: Addressing library creation challenges from recent Liberty extensions. 474-479

Advanced wireless design

• 
  Christian Sauer, Matthias Gries, Hans-Peter Löb: SystemClick: a domain-specific framework for early exploration using functional performance models. 480-485
• 
  Joon Goo Lee, Dongha Jung, Jiho Chu, Seokjoong Hwang, Jong-Kook Kim, Janam Ku, Seon Wook Kim: Applying passive RFID system to wireless headphones for extreme low power consumption. 486-491
• 
  Shreyas Sen, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee: Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems. 492-497
• 
  Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud: Automated design of tunable impedance matching networks for reconfigurable wireless applications. 498-503

Manufacturing aware design and design aware manufacturing

• 
  Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. 504-509
• 
  Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang: Predictive formulae for OPC with applications to lithography-friendly routing. 510-515
• 
  Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao: Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. 516-521
• 
  Siew-Hong Teh, Chun-Huat Heng, Arthur Tay: Design-process integration for performance-based OPC framework. 522-527

Advances in sequential optimization

• 
  Jia Wang, Hai Zhou: An efficient incremental algorithm for min-area retiming. 528-533
• 
  Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Scalable min-register retiming under timing and initializability constraints. 534-539
• 
  Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton: Merging nodes under sequential observability. 540-545
• 
  Yousra Alkabani, Farinaz Koushanfar: N-variant IC design: methodology and applications. 546-551

Panel

• 
  Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman: Verifying really complex systems: on earth and beyond. 552-553

Beyond the die - packaging and die stacking

• 
  Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. 554-559
• 
  Krishna Bharath, Ege Engin, Madhavan Swaminathan: Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM. 560-565
• 
  Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong: Topological routing to maximize routability for package substrate. 566-569
• 
  Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng: Low power passive equalizer optimization using tritonic step response. 570-573

Special session: ESL methodologies for platform-based synthesis

• 
  Hristo Nikolov, Mark Thompson, Todor Stefanov, Andy D. Pimentel, Simon Polstra, R. Bose, Claudiu Zissulescu, Ed F. Deprettere: Daedalus: toward composable multimedia MP-SoC design. 574-579
• 
  Christian Haubelt, Thomas Schlichter, Joachim Keinert, Michael Meredith: SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models. 580-585
• 
  Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, A. Nakamura, Dai Araki, Y. Nishihara: Specify-explore-refine (SER): from specification to implementation. 586-591

Special session: wireless: business meets technology

• 
  Risto Savolainen, Tero Rissa: Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation. 592
• 
  Matt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic: Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration. 593

Leakage analysis and optimization

• 
  Tao Li, Wenjun Zhang, Zhiping Yu: Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification. 594-599
• 
  Seungwhun Paik, Youngsoo Shin: Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. 600-605
• 
  Yousra Alkabani, Tammara Massey, Farinaz Koushanfar, Miodrag Potkonjak: Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability. 606-609
• 
  Min Ni, Seda Ogrenci Memik: Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. 610-613

Design methods for on-chip communication

• 
  Ümit Y. Ogras, Radu Marculescu, Diana Marculescu: Variation-adaptive feedback control for networks-on-chip with multiple clock domains. 614-619
• 
  Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. Kandemir: Application mapping for chip multiprocessors. 620-625
• 
  Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang: Concurrent topology and routing optimization in automotive network integration. 626-629
• 
  Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai: A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. 630-633

Panel

• 
  Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky: Keeping hot chips cool: are IC thermal problems hot air? 634-635

New advances in logic synthesis

• 
  Ruei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung: Bi-decomposing large Boolean functions via interpolation and satisfiability solving. 636-641
• 
  Afshin Abdollahi: Signature based Boolean matching in the presence of don't cares. 642-647
• 
  Weikang Qian, Marc D. Riedel: The synthesis of robust polynomial arithmetic with stochastic logic. 648-653
• 
  Aaron P. Hurst: Automatic synthesis of clock gating logic with controlled netlist perturbation. 654-657
• 
  Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed: A new paradigm for synthesis and propagation of clock gating conditions. 658-663

Special session: 3-D semiconductor integration & packaging

• 
  Ted Vucurevich: 3-D semiconductor's: more from Moore. 664
• 
  Jerry Bautista: Tera-scale computing and interconnect challenges. 665-667
• 
  Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller: Design and CAD for 3D integrated circuits. 668-673
• 
  Wilfried Haensch: Why should we do 3D integration? 674-675

Statistical timing analysis

• 
  Vineeth Veetil, Dennis Sylvester, David Blaauw: Efficient Monte Carlo based incremental statistical timing analysis. 676-681
• 
  Zuochang Ye, Zhenhai Zhu, Joel R. Phillips: Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis. 682-687
• 
  Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar: A framework for block-based timing sensitivity analysis. 688-693
• 
  Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen: Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. 694-697
• 
  Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu: Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. 698-701

Performance driven layout optimization

• 
  Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: An integrated nonlinear placement framework with congestion and porosity aware buffer planning. 702-707
• 
  Zhanyuan Jiang, Weiping Shi: Circuit-wise buffer insertion and gate sizing algorithm with scalability. 708-713
• 
  Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu: Type-matching clock tree for zero skew clock gating. 714-719
• 
  Anand Rajaram, David Z. Pan: Robust chip-level clock tree synthesis for SOC designs. 720-723
• 
  Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert: Path smoothing via discrete optimization. 724-727

Power and thermal considerations in single- and multi-core systems

• 
  Hwisung Jung, Peng Rong, Massoud Pedram: Stochastic modeling of a thermally-managed multi-core system. 728-733
• 
  Inchoon Yeo, Chih Chun Liu, Eun Jung Kim: Predictive dynamic thermal management for multicore systems. 734-739
• 
  Yan Gu, Samarjit Chakraborty: Control theory-based DVS for interactive 3D games. 740-745
• 
  Wei Huang, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, Kevin Skadron: Many-core design from a thermal perspective. 746-749
• 
  Xiangrong Zhou, Chenjie Yu, Peter Petrov: Compiler-driven register re-assignment for register file power-density and temperature reduction. 750-753

Multi-core design tools and architectures

• 
  Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda: MAPS: an integrated framework for MPSoC application parallelization. 754-759
• 
  Mohammad Abdullah Al Faruque, Rudolf Krist, Jörg Henkel: ADAM: run-time agent-based distributed application mapping for on-chip communication. 760-765
• 
  Chenjie Yu, Peter Petrov: Latency and bandwidth efficient communication through system customization for embedded multiprocessors. 766-771
• 
  David Tarjan, Michael Boyer, Kevin Skadron: Federation: repurposing scalar cores for out-of-order instruction issue. 772-775
• 
  Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung: ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. 776-779

Reconfigurable architecture optimizations

• 
  John D. Davis, Zhangxi Tan, Fang Yu, Lintao Zhang: A practical reconfigurable hardware accelerator for Boolean satisfiability solvers. 780-785
• 
  Somnath Paul, Swarup Bhunia: Reconfigurable computing using content addressable memory for improved performance and resource usage. 786-791
• 
  Ian Kuon, Jonathan Rose: Automated transistor sizing for FPGA architecture exploration. 792-795
• 
  Stephen Bijansky, Adnan Aziz: TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. 796-799

Special session: formal verification: dude or dud? experiences from the trenches

• 
  Raj S. Mitra: Strategies for mainstream usage of formal verification. 800-805
• 
  Robert Beers: Pre-RTL formal verification: an intel experience. 806-811
• 
  Kelvin Ng: Challenges in using system-level models for RTL verification. 812-815
• 
  Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla: Leveraging sequential equivalence checking to enable system-level to RTL flows. 816-821

Random topics in testing

• 
  Kanupriya Gulati, Sunil P. Khatri: Towards acceleration of fault simulation using graphics processing units. 822-827
• 
  Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding: Scan chain clustering for test power reduction. 828-833
• 
  Lin Huang, Feng Yuan, Qiang Xu: On reliable modular testing with vulnerable test access mechanisms. 834-839
• 
  Sudhakar M. Reddy, Irith Pomeranz, Chen Liu: On tests to detect via opens in digital CMOS circuits. 840-845

Securing and debugging embedded systems

• 
  Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov: Protecting bus-based hardware IP by secret sharing. 846-851
• 
  Piti Piyachon, Yan Luo: Design of high performance pattern matching engine through compact deterministic finite automata. 852-857
• 
  Krutartha Patel, Sri Parameswaran: SHIELD: a software hardware design methodology for security and reliability of MPSoCs. 858-861
• 
  Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang: A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer. 862-865
• 
  Ming-Chang Hsieh, Chih-Tsun Huang: An embedded infrastructure of debug and trace interface for the DSP platform. 866-871

Topics in power and thermal management

• 
  Suman Kalyan Mandal, Praveen Bhojwani, Saraju P. Mohanty, Rabi N. Mahapatra: IntellBatt: towards smarter battery design. 872-877
• 
  Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik: A power and temperature aware DRAM architecture. 878-883
• 
  Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara: Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. 884-889
• 
  Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross: Temperature management in multiprocessor SoCs using online learning. 890-893
• 
  Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull: DVFS in loop accelerators using BLADES. 894-897

Panel

• 
  Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh: DFM in practice: hit or hype? 898-899

Physical effects of variability

• 
  Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao: Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. 900-905
• 
  Tarek A. El-Moselhy, Ibrahim M. Elfadel, David Widiger: Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters. 906-911
• 
  Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. 912-917

Soft error in scaled CMOS design

• 
  Rajesh Garg, Charu Nagpal, Sunil P. Khatri: A fast, analytical estimator for the SEU-induced pulse width in combinational designs. 918-923
• 
  Smita Krishnaswamy, Igor L. Markov, John P. Hayes: On the role of timing masking in reliable logic circuit design. 924-929
• 
  Juan Antonio Maestro, Pedro Reviriego: Study of the effects of MBUs on the reliability of a 150 nm SRAM device. 930-935

Advances in verification of abstract (pre-RTL) models

• 
  Sudipta Kundu, Malay K. Ganai, Rajesh Gupta: Partial order reduction for scalable testing of systemC TLM designs. 936-941
• 
  Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, Basant Dwivedi, Antara Ghosh: Construction of concrete verification models from C++. 942-947
• 
  Alper Sen, Vinit Ogale, Magdy S. Abadir: Predictive runtime verification of multi-processor SoCs in SystemC. 948-953

Design space exploration

• 
  Juan Hamers, Lieven Eeckhout: Automated hardware-independent scenario identification. 954-959
• 
  Henry Cook, Kevin Skadron: Predictive design space exploration using genetically programmed response surfaces. 960-965
• 
  Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary: Efficient system design space exploration using machine learning techniques. 966-969
• 
  Zhanpeng Jin, Allen C. Cheng: Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case study. 970-973

Noise reliability enhancement

• 
  Ravikishore Gandikota, David Blaauw, Dennis Sylvester: Modeling crosstalk in statistical static timing analysis. 974-979
• 
  Hailin Jiang, Malgorzata Marek-Sadowska: Power gating scheduling for power/ground noise reduction. 980-985
• 
  Chunjie Duan, Chengyu Zhu, Sunil P. Khatri: Forbidden transition free crosstalk avoidance CODEC design. 986-991

Panel

• 
  Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye: Custom is from Venus and synthesis from Mars. 992