45. DAC 2008: Anaheim, CA, USA

iDesign I

Special session: enabling concurrency in EDA


Analog performance modeling and synthesis

Novel techniques in embedded processor design


Special session: student design contest



Formal verification technology

Layout techniques for modern chip designs

Application mapping and power efficiency

Variation-aware design

iDesign II

Multi-core simulation, mixed-signal power optimization and nanodevices

Experiences and advances in formal and dynamic verification

Emerging nano/biotechnologies

Cache optimization and embedded systems modeling


Analytical modeling and simulation of complex processing systems

Special session: wild and crazy ideas


Diagnosis and debug

Architectural and precision optimization in high-level synthesis

Extraction, interconnect and timing

Architectures for on-chip communication

Special session: CMOS gate modeling for timing, noise, and power: rapidly changing paradigm

Advanced wireless design

Manufacturing aware design and design aware manufacturing

Advances in sequential optimization


Beyond the die - packaging and die stacking

Special session: ESL methodologies for platform-based synthesis

Special session: wireless: business meets technology

Leakage analysis and optimization

Design methods for on-chip communication


New advances in logic synthesis

Special session: 3-D semiconductor integration & packaging

Statistical timing analysis

Performance driven layout optimization

Power and thermal considerations in single- and multi-core systems

Multi-core design tools and architectures

Reconfigurable architecture optimizations

Special session: formal verification: dude or dud? experiences from the trenches

Random topics in testing

Securing and debugging embedded systems

Topics in power and thermal management


Physical effects of variability

Soft error in scaled CMOS design

Advances in verification of abstract (pre-RTL) models

Design space exploration

Noise reliability enhancement