41. DAC 2004:
San Diego, CA, USA Sharad Malik , Limor Fix , Andrew B. Kahng (Eds.):
Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004.
ACM 2004, ISBN 1-58113-828-8 Panel
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Hot Leakage
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conf/dac/VassighiKNSYLCSD04 export record as
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Clock Routing and Buffering
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Tools and Strategies for Dynamic Verification
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Timing-Driven System Synthesis
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Kai Kapp ,
Viktor K. Sabelfeld :
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis.
61-66
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Reliable System-on-a-chip Design in the Nanometer Era
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Panel
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conf/dac/StrojwasCGHKLNPT04
Power Modeling and Optimization for Embedded Systems
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Chun-Gi Lyuh ,
Taewhan Kim :
Memory access scheduling and binding considering energy minimization in multi-bank memory systems.
81-86
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Performance Evaluation and Run Time Support
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Javier Resano ,
Daniel Mozos :
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware.
119-124
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Mahmut T. Kandemir :
LODS: locality-oriented dynamic scheduling for on-chip multiprocessors.
125-128
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Advances in Analog Circuit and Layout Synthesis
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conf/dac/BhattacharyaJHS04 export record as
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Power Grid Design and Analysis Techniques
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Su-Wei Wu ,
Yao-Wen Chang :
Efficient power/ground network analysis for power integrity-driven design methodology.
177-180
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Panel
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Methods for A Priori Feasible Layout Generation
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Abstraction Techniques for Functional Verification
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conf/dac/ParthasarathyICW04 export record as
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Memory and Network Optimization in Embedded Designs
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conf/dac/FrancescoMABCM04 export record as
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Business Day Session
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The Future of Timing Closure
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David S. Kung :
Timing closure for low-FO4 microprocessor design.
265-266
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Panel
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conf/dac/BacchiniDBBNIY04
Design Space Exploration and Scheduling for Embedded Software
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Advances in Accelerated Simulation
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Design for Manufacturing
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Statistical Timing Analysis
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conf/dac/VisweswariahRKWN04 export record as
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Panel
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conf/dac/BacchiniPBPBCB04
New Ideas in Placement
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conf/dac/AntonelliCDHKKMN04
Model Order Reduction and Variational Techniques for Parasitic Analysis
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Compilation Techniques for Embedded Applications
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Platform-based System Design
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Gary Smith :
Platform based design: does it answer the entire SoC challenge?
407
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Mark Hopkins :
Nomadic platform approach for wireless mobile multimedia.
408
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conf/dac/Sangiovanni-VincentelliCBS04 export record as
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Max Baron :
Trends in the use of re-configurable platforms.
415
Innovations in Logic Synthesis
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Yield Estimation and Optimization
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High-level Techniques for Signal Processing
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Advanced Test Solutions
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Panel
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conf/dac/GoldmanKBBBCSV04
Advances in Boolean Analysis Techniques
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Panel
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Power Optimization for Real-Time and Media-Rich Embedded Systems
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Latency Tolerance and Asynchronous Design
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New Technologies in System Design
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Samar Abdi ,
Daniel Gajski :
Automatic generation of equivalent architecture model from functional specification.
608-613
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BioMEMS
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Panel
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conf/dac/RutenbarBMPPSW04
Floorplanning
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conf/dac/EkpanyapongMWLL04 export record as
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Issues in Timing Analysis
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ISSCC Highlights
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conf/dac/ClabesFSDCPDMPFSLGWSRGRKMD04 Joachim G. Clabes ,
Joshua Friedrich ,
Mark Sweet ,
Jack DiLullo ,
Sam G. Chu ,
Donald W. Plass ,
James Dawson ,
Paul Muench ,
Larry Powell ,
Michael S. Floyd ,
Balaram Sinharoy ,
Mike Lee ,
Michael Goulet ,
James Wagoner ,
Nicole S. Schwartz ,
Stephen L. Runyon ,
Gary Gorman ,
Phillip Restle ,
Ronald N. Kalla ,
Joseph McGill ,
J. Steve Dodson :
Design and implementation of the POWER5 microprocessor.
670-672
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conf/dac/TakayanagiSPSL04 export record as
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conf/dac/DeleganesBGKSW04
Multiprocessor SoC MPSoC Solutions/Nightmare
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Wayne Wolf :
The future of multiprocessor systems-on-chips.
681-685
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Timing Issues in Placement
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Design Methodologies for ASIPs
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Pan Yu ,
Tulika Mitra :
Characterizing embedded applications for instruction-set extensible processors.
723-728
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FPGA-Based Systems
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conf/dac/SelvakkumaranRRK04 export record as
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Security as a New Dimension in Embedded System Design
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Leakage Power Optimization
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Interconnect Extraction
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Shu Yan ,
Vivek Sarin ,
Weiping Shi :
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics.
788-793
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Yuichi Tanji ,
Hideki Asai :
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects.
810-813
New Frontiers in Logic Synthesis
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conf/dac/TummeltshammerHP04 export record as
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Pawel Kerntopf :
A new heuristic algorithm for reversible logic synthesis.
834-837
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Numerical Techniques for Simulation
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Baolin Yang ,
Bruce McGaughy :
An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modeling.
864-867
Energy and Thermal-Aware Design
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Noise-Tolerant Design and Analysis Techniques
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New Tools and Methods for Future Embedded SoC
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New Scan-Based Test Techniques
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Irith Pomeranz :
On the generation of scan-based test sets with reachable states for testing under functional operation conditions.
928-933
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CAD for Reconfigurable Computing
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