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ORCIDSambuddha Bhattacharya
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2010 – 2019
- 2015
[c15]Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. VLSID 2015: 186-191- 2014
- [c14]Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala:
Fixing Double Patterning violations with look-ahead. ASP-DAC 2014: 149-154 - 2013
- [c13]Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Automatic design rule correction in presence of multiple grids and track patterns. DAC 2013: 26:1-26:6
2000 – 2009
- 2009
- [c12]Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design 2009: 137-142 - 2008
- [j3]Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi:
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 791-802 (2008) - [c11]Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384 - [c10]Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455 - 2006
- [j2]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi:
Multilevel symmetry-constraint generation for retargeting large analog layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 945-960 (2006) - [c9]Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi:
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. ICCAD 2006: 342-348 - 2005
- [c8]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi:
Template-driven parasitic-aware optimization of analog integrated circuit layouts. DAC 2005: 644-647 - [c7]Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi:
Automatic Device Layout Generation for Analog Layout Retargeting. VLSI Design 2005: 457-462 - 2004
- [c6]Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, Chuanjin Richard Shi:
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ASP-DAC 2004: 163-168 - [c5]Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi:
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. ASP-DAC 2004: 394-399 - [c4]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi:
Hierarchical extraction and verification of symmetry constraints for analog layout automation. ASP-DAC 2004: 400-405 - [c3]Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi:
Correct-by-construction layout-centric retargeting of large analog designs. DAC 2004: 139-144 - 2003
- [j1]Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi:
IPRAIL - intellectual property reuse-based analog IC layout automation. Integr. 36(4): 237-262 (2003) - [c2]Sambuddha Bhattacharya, Chuanjin Richard Shi:
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. ISCAS (4) 2003: 660-663 - [c1]Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi:
Automatic analog layout retargeting for new processes and device sizes. ISCAS (4) 2003: 704-707
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