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Zaher S. Andraus

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2000 – 2009

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2009
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Zaher S. Andraus:
Automatic Formal Verification of Control Logic in Hardware Designs. University of Michigan, USA, 2009
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Mark H. Liffiton, Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah:
A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas. Constraints An Int. J. 14(4): 415-442 (2009)
2008
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Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah:
Reveal: A Formal Verification Tool for Verilog Designs. LPAR 2008: 343-352
2006
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Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah:
Refinement strategies for verification methods based on datapath abstraction. ASP-DAC 2006: 19-24
2005
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Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah:
A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas. SAT 2005: 467-474
2004
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Zaher S. Andraus, Karem A. Sakallah:
Automatic abstraction and verification of verilog models. DAC 2004: 218-223
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Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov:
AMUSE: a minimally-unsatisfiable subformula extractor. DAC 2004: 518-523

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