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ORCIDLouis K. Scheffer
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2020 – today
- 2022
[j7]Stephen M. Plaza, Jody Clements, Tom Dolafi, Lowell A. Umayam, Nicole N. Neubarth, Louis K. Scheffer, Stuart E. Berg
:
neuPrint: An open access tool for EM connectomics. Frontiers Neuroinformatics 16 (2022)- 2021
- [c30]Louis K. Scheffer:
A Lifetime of ICs, and Cross-field Exploration: ISPD 2021 Lifetime Achievement Award Bio. ISPD 2021: 99-100 - [c29]Louis K. Scheffer:
The Physical Design of Biological Systems - Insights from the Fly Brain. ISPD 2021: 101-108 - 2020
- [c28]Louis K. Scheffer:
INVITED: Computational Methods of Biological Exploration. DAC 2020: 1-4
2010 – 2019
- 2018
- [c27]Louis K. Scheffer:
Insights from Biology: Low Power Circuits in the Fruit Fly. ISLPED 2018: 54:1-54:3 - 2016
- [i3]Gary B. Huang, Louis K. Scheffer, Stephen M. Plaza:
Fully-Automatic Synapse Prediction and Validation on a Large Data Set. CoRR abs/1604.03075 (2016) - 2014
- [c26]Louis Scheffer:
Lessons from the neurons themselves. ASP-DAC 2014: 197-200 - [c25]Toufiq Parag, Stephen M. Plaza, Louis Scheffer:
Small Sample Learning of Superpixel Classifiers for EM Segmentation. MICCAI (1) 2014: 389-397 - [r2]Arjun Bharioke, Louis K. Scheffer, Dmitri B. Chklovskii, Ian A. Meinertzhagen:
Drosophila Connectome. Encyclopedia of Computational Neuroscience 2014 - [i2]Toufiq Parag, Stephen Plaza, Louis Scheffer:
Small Sample Learning of Superpixel Classifiers for EM Segmentation- Extended Version. CoRR abs/1406.1774 (2014) - 2013
- [j6]Tao Hu, Juan Nunez-Iglesias, Shiv Naga Prasad Vitaladevuni, Lou Scheffer, Shan Xu, Mehdi Bolorizadeh, Harald F. Hess, Richard Fetter, Dmitri B. Chklovskii:
Electron Microscopy Reconstruction of Brain Structure Using Sparse Representations Over Learned Dictionaries. IEEE Trans. Medical Imaging 32(12): 2179-2188 (2013) - [c24]Lou Scheffer:
Keynote talk: Deciphering the brain, cousin to the chip. VLSI Design 2013 - 2012
- [c23]Louis Scheffer:
Design tools for artificial nervous systems. DAC 2012: 717-722 - [i1]Tao Hu, Juan Nunez-Iglesias, Shiv Naga Prasad Vitaladevuni, Lou Scheffer, Shan Xu, Mehdi Bolorizadeh, Harald F. Hess, Richard Fetter, Dmitri B. Chklovskii:
Super-resolution using Sparse Representations over Learned Dictionaries: Reconstruction of Brain Structure using Electron Microscopy. CoRR abs/1210.0564 (2012) - 2011
- [c22]Daniel Glasner, Tao Hu, Juan Nunez-Iglesias, Lou Scheffer, Shan Xu, Harald F. Hess, Richard Fetter, Dmitri B. Chklovskii, Ronen Basri:
High Resolution Segmentation of Neuronal Tissues from Low Depth-Resolution EM Imagery. EMMCVPR 2011: 261-272 - 2010
- [c21]Ashok Veeraraghavan, Alex V. Genkin, Shiv Naga Prasad Vitaladevuni, Lou Scheffer, Shan Xu, Harald F. Hess, Richard Fetter, Marco Cantoni, Graham Knott, Dmitri B. Chklovskii:
Increasing depth resolution of electron microscopy of neural circuits using sparse tomographic reconstruction. CVPR 2010: 1767-1774 - [c20]Louis Scheffer:
Physical design of biological systems. ISPD 2010: 1 - [c19]Patrick Groeneveld, Louis Scheffer, Dirk Stroobandt:
SLIP: 10 years ago and 10 years from now. SLIP 2010: 67-68 - [e5]Louis Scheffer, Joel R. Phillips, Alan J. Hu:
2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010. IEEE 2010, ISBN 978-1-4244-8192-7 [contents]
2000 – 2009
- 2008
- [j5]David T. Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 589-607 (2008) - [r1]Louis K. Scheffer:
Industrial Floorplanning and Prototyping. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j4]Igor L. Markov, Louis Scheffer, Dirk Stroobandt:
Special issue on System-Level Interconnect Prediction. Integr. 40(4): 381 (2007) - [c18]Louis Scheffer:
CAD Implications of New Interconnect Technologies. DAC 2007: 576-581 - [c17]Louis Scheffer, Lars Liebmann, Riko Rakojcic, David White:
Rules vs tools: what's the right way to address IC manufacturing complexity? ISPD 2007: 75-76 - [c16]David Cross, Eric Nequist, Louis Scheffer:
A DFM aware, space based router. ISPD 2007: 171-172 - 2006
- [c15]Louis Scheffer:
An overview of on-chip interconnect variation. SLIP 2006: 27-28 - [e4]Louis Scheffer:
Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006. ACM 2006, ISBN 1-59593-299-2 [contents] - 2005
- [e3]Patrick Groeneveld, Louis Scheffer:
Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005. ACM 2005, ISBN 1-59593-021-3 [contents] - 2004
- [c14]Louis Scheffer:
Physical CAD changes to incorporate design for lithography and manufacturability. ASP-DAC 2004: 768-773 - [c13]Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah:
Is statistical timing statistically significant? DAC 2004: 498 - [c12]Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester:
The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61 - [e2]Louis Scheffer, Igor L. Markov:
The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings. ACM 2004, ISBN 1-58113-818-0 [contents] - 2003
- [j3]Louis Scheffer:
Some conditions under which hierarchical verification is O(N). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 643-646 (2003) - [c11]Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf:
Nanometer design: place your bets. DAC 2003: 546-547 - [c10]Louis Scheffer:
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips. PATMOS 2003: 194 - [e1]Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha:
The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings. ACM 2003, ISBN 1-58113-627-7 [contents] - 2002
- [c9]Louis Scheffer:
Methodologies and Tools for Pipelined On-Chip Interconnect. ICCD 2002: 152-157 - [c8]Louis Scheffer:
Explicit computation of performance as a function of process variation. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 1-8 - 2001
- [j2]Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen:
Timing- and crosstalk-driven area routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 528-544 (2001) - [c7]Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang:
Panel: Is Nanometer Design Under Control? DAC 2001: 591-592 - 2000
- [c6]Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer:
Design closure (panel session): hope or hype? DAC 2000: 176-177 - [c5]Lou Scheffer:
What is the Appropriate Model for Crosstalk Control? SBCCI 2000: 315-320 - [c4]Louis Scheffer, Eric Nequist:
Why interconnect prediction doesn't work. SLIP 2000: 139-144
1990 – 1999
- 1998
- [c3]Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen:
Timing and Crosstalk Driven Area Routing. DAC 1998: 378-381 - 1997
- [c2]Louis Scheffer:
A roadmap of CAD tool changes for sub-micron interconnect problems. ISPD 1997: 104-109
1980 – 1989
- 1986
- [j1]Louis K. Scheffer, Ronny Soetarman:
Hierarchical Analysis of IC Artwork with User-Defined Rules. IEEE Des. Test 3(1): 66-74 (1986) - 1985
- [c1]Louis Scheffer, Ronny Soetarman:
Hierarchical analysis of IC artwork with user defined abstraction rules. DAC 1985: 293-298
Coauthor Index
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