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"Logic verification using binary decision diagrams in a logic synthesis ..."

Sharad Malik et al. (1988)

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DOI: 10.1109/ICCAD.1988.122451

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD 1988: 6-9

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