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ORCIDGeorge A. Constantinides
George Anthony Constantinides
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- affiliation: Imperial College London, UK
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2020 – today
- 2024
[c203]Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides:
Combining Power and Arithmetic Optimization via Datapath Rewriting. ARITH 2024: 24-31- [c202]Martin Langhammer
, George A. Constantinides:
A Statically and Dynamically Scalable Soft GPGPU. FPGA 2024: 165-175 - [c201]Marta Andronic, George A. Constantinides:
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. FPL 2024: 140-148 - [c200]Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides:
Exploring FPGA designs for MX and beyond. FPL 2024: 304-310 - [c199]Quentin Corradi, John Wickerson, George A. Constantinides:
Automated Feature Testing of Verilog Parsers using Fuzzing (Registered Report). FUZZING 2024: 70-79 - [c198]Martin Langhammer, George A. Constantinides:
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. HEART 2024: 44-52 - [c197]Cheng Zhang, Jianyi Cheng, George Anthony Constantinides, Yiren Zhao:
LQER: Low-Rank Quantization Error Reconstruction for LLMs. ICML 2024 - [i40]Martin Langhammer, George A. Constantinides:
A Statically and Dynamically Scalable Soft GPGPU. CoRR abs/2401.04261 (2024) - [i39]Cheng Zhang, Jianyi Cheng, George A. Constantinides, Yiren Zhao:
LQER: Low-Rank Quantization Error Reconstruction for LLMs. CoRR abs/2402.02446 (2024) - [i38]Marta Andronic, George A. Constantinides:
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. CoRR abs/2403.00849 (2024) - [i37]Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides:
Combining Power and Arithmetic Optimization via Datapath Rewriting. CoRR abs/2404.12336 (2024) - [i36]Martin Langhammer, George A. Constantinides:
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. CoRR abs/2406.03227 (2024) - [i35]Samuel Coward, Theo Drane, George A. Constantinides:
ROVER: RTL Optimization via Verified E-Graph Rewriting. CoRR abs/2406.12421 (2024) - [i34]Zixi Zhang, Cheng Zhang, Xitong Gao, Robert D. Mullins, George A. Constantinides, Yiren Zhao:
Unlocking the Global Synergies in Low-Rank Adapters. CoRR abs/2406.14956 (2024) - [i33]Yuang Chen, Cheng Zhang, Xitong Gao, Robert D. Mullins, George A. Constantinides, Yiren Zhao:
Optimised Grouped-Query Attention Mechanism for Transformers. CoRR abs/2406.14963 (2024) - [i32]Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides:
Exploring FPGA designs for MX and beyond. CoRR abs/2407.01475 (2024) - 2023
- [j74]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Horizon-Independent Preconditioner Design for Linear Predictive Control. IEEE Trans. Autom. Control. 68(1): 580-587 (2023) - [j73]Jianyi Cheng, Estíbaliz Fraca, John Wickerson, George A. Constantinides:
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers 72(11): 3300-3313 (2023) - [j72]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. 22(6): 105:1-105:19 (2023) - [j71]Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides:
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(4): 55:1-55:32 (2023) - [j70]Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis:
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(4): 57:1-57:25 (2023) - [c196]Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac:
Multiplier Optimization via E-Graph Rewriting. ACSSC 2023: 1528-1533 - [c195]Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing. CF 2023: 393-394 - [c194]Samuel Coward, George A. Constantinides, Theo Drane:
Automating Constraint-Aware Datapath Optimization using E-Graphs. DAC 2023: 1-6 - [c193]Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
A Parametrizable Template for Approximate Logic Synthesis. DSN-W 2023: 175-178 - [c192]Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. DSN-W 2023: 199-202 - [c191]Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao:
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? EMNLP 2023: 9988-10006 - [c190]Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides:
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. FCCM 2023: 121-132 - [c189]Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides:
Datapath Verification via Word-Level E-Graph Rewriting. FMCAD 2023: 92-100 - [c188]Martin Langhammer, George A. Constantinides:
eGPU: A 750 MHz Class Soft GPGPU for FPGA. FPL 2023: 277-282 - [c187]Marta Andronic, George A. Constantinides:
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. ICFPT 2023: 60-68 - [c186]Benjamin Ramhorst, Vladimir Loncar, George A. Constantinides:
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. ICFPT 2023: 282-283 - [c185]Samuel Coward, George A. Constantinides, Theo Drane:
Combining E-Graphs with Abstract Interpretation. SOAP@PLDI 2023: 1-7 - [i31]Samuel Coward, George A. Constantinides, Theo Drane:
Automating Constraint-Aware Datapath Optimization using E-Graphs. CoRR abs/2303.01839 (2023) - [i30]Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides:
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. CoRR abs/2304.08400 (2023) - [i29]Martin Langhammer, George A. Constantinides:
eGPU: A 750 MHz Class Soft GPGPU for FPGA. CoRR abs/2307.08378 (2023) - [i28]Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides:
Datapath Verification via Word-Level E-Graph Rewriting. CoRR abs/2308.00431 (2023) - [i27]Benjamin Ramhorst, George A. Constantinides, Vladimir Loncar:
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. CoRR abs/2308.05170 (2023) - [i26]Marta Andronic, George A. Constantinides:
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. CoRR abs/2309.02334 (2023) - [i25]Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao:
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? CoRR abs/2310.05079 (2023) - [i24]Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac:
Multiplier Optimization via E-Graph Rewriting. CoRR abs/2312.06004 (2023) - 2022
- [j69]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides:
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71(4): 933-946 (2022) - [j68]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [j67]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 840-853 (2022) - [j66]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis. ACM Trans. Design Autom. Electr. Syst. 27(4): 30:1-30:26 (2022) - [c184]Samuel Coward, George A. Constantinides, Theo Drane:
Automatic Datapath Optimization using E-Graphs. ARITH 2022: 43-50 - [c183]Jianyi Cheng, John Wickerson, George A. Constantinides:
Dynamic C-Slow Pipelining for HLS. FCCM 2022: 1-10 - [c182]Jianyi Cheng, John Wickerson, George A. Constantinides:
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA 2022: 89-100 - [c181]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA 2022: 101-111 - [c180]Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides:
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL 2022: 235-242 - [c179]Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson:
Dynamic Inter-Block Scheduling for HLS. FPL 2022: 243-252 - [c178]Xuefei He, Jianyi Cheng, George A. Constantinides:
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. FPT 2022: 1-4 - [c177]Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides:
MIDAS: Mutual Information Driven Approximate Synthesis. ISVLSI 2022: 50-55 - [d2]Dovydas Joksas, Erwei Wang, Nikolaos Barmpatsalos, Wing H. Ng, Anthony J. Kenyon, George A. Constantinides, Adnan Mehonic:
Generated Data for the Manuscript "Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks". Version 1.1. Zenodo, 2022 [all versions]
- [i23]Benjamin Biggs, Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
High-level Synthesis using the Julia Language. CoRR abs/2201.11522 (2022) - [i22]Samuel Coward, George A. Constantinides, Theo Drane:
Abstract Interpretation on E-Graphs. CoRR abs/2203.09191 (2022) - [i21]Samuel Coward, George A. Constantinides, Theo Drane:
Automatic Datapath Optimization using E-Graphs. CoRR abs/2204.11478 (2022) - [i20]Samuel Coward, George A. Constantinides, Theo Drane:
Combining E-Graphs with Abstract Interpretation. CoRR abs/2205.14989 (2022) - 2021
- [j65]He Li, Ian McInerney, James J. Davis, George A. Constantinides:
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. IEEE Trans. Computers 70(7): 1074-1080 (2021) - [j64]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Global Analysis of C Concurrency in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 24-37 (2021) - [c176]Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides:
Learning Boolean Circuits from Examples for Approximate Logic Synthesis. ASP-DAC 2021: 524-529 - [c175]George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia:
Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CAV (2) 2021: 626-650 - [c174]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Scheduling in High-Level Synthesis. FCCM 2021: 195-203 - [c173]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Optimization for High-Level Synthesis. FPGA 2021: 145 - [c172]Jianyi Cheng, John Wickerson, George A. Constantinides:
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL 2021: 341-346 - [c171]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys 2021: 37-38 - [d1]Dovydas Joksas, Erwei Wang, Nikolaos Barmpatsalos, Wing H. Ng, Anthony J. Kenyon, George A. Constantinides, Adnan Mehonic:
Generated Data for the Manuscript "Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks". Version 1.0. Zenodo, 2021 [all versions] - [i19]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. CoRR abs/2102.04270 (2021) - [i18]George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia:
Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CoRR abs/2105.13217 (2021) - [i17]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR abs/2112.02346 (2021) - [i16]Dovydas Joksas, Erwei Wang, Nikolaos Barmpatsalos, Wing H. Ng, Anthony J. Kenyon, George A. Constantinides, Adnan Mehonic:
Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks. CoRR abs/2112.06887 (2021) - 2020
- [j63]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda:
Approximate Logic Synthesis: A Survey. Proc. IEEE 108(12): 2195-2213 (2020) - [j62]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers 69(12): 1795-1808 (2020) - [j61]He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 516-529 (2020) - [c170]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298 - [c169]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Precise Pointer Analysis in High-Level Synthesis. FPL 2020: 220-224 - [i15]He Li, Ian McInerney, James J. Davis, George A. Constantinides:
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. CoRR abs/2006.09427 (2020) - [i14]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Horizon-independent Preconditioner Design for Linear Predictive Control. CoRR abs/2010.08572 (2020)
2010 – 2019
- 2019
- [j60]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019) - [j59]Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 719-732 (2019) - [j58]Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides:
Automatic Software and Computing Hardware Codesign for Predictive Control. IEEE Trans. Control. Syst. Technol. 27(5): 2295-2304 (2019) - [c168]Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides:
A Probabilistic Approach to Floating-Point Arithmetic. ACSSC 2019: 596-602 - [c167]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Modeling Round-off Error in the Fast Gradient Method for Predictive Control. CDC 2019: 4331-4336 - [c166]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC 2019: 40 - [c165]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM 2019: 26-34 - [c164]Florian Faissole, George A. Constantinides, David B. Thomas:
Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. FCCM 2019: 315 - [c163]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides:
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA 2019: 142-151 - [c162]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT 2019: 45-53 - [c161]Ameer M. S. Abdelhadi, Christos-Savvas Bouganis, George A. Constantinides:
Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization. FPT 2019: 90-98 - [i13]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i12]Ian McInerney, Eric C. Kerrigan, George A. Constantinides:
Bounding Computational Complexity under Cost Function Scaling in Predictive Control. CoRR abs/1902.02221 (2019) - [i11]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR abs/1904.00938 (2019) - [i10]George A. Constantinides:
Rethinking Arithmetic for Deep Neural Networks. CoRR abs/1905.02438 (2019) - [i9]He Li, James J. Davis, John Wickerson, George A. Constantinides:
ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR abs/1910.00271 (2019) - [i8]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR abs/1910.10075 (2019) - [i7]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR abs/1910.12625 (2019) - [i6]Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides:
A Probabilistic Approach to Floating-Point Arithmetic. CoRR abs/1912.00867 (2019) - 2018
- [j57]Nadesh Ramanathan, John Wickerson, George A. Constantinides:
Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware. IEEE Trans. Computers 67(7): 992-1006 (2018) - [j56]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1802-1815 (2018) - [j55]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c160]Nicolas Brisebarre, George A. Constantinides, Milos Ercezovac, Silviu-Ioan Filip, Matei Istoan, Jean-Michel Muller:
A High Throughput Polynomial and Rational Function Approximations Evaluator. ARITH 2018: 99-106 - [c159]He Li, James J. Davis, John Wickerson, George A. Constantinides:
Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH 2018: 107-114 - [c158]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c157]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Concurrency-Aware Thread Scheduling for High-Level Synthesis. FCCM 2018: 101-108 - [c156]Georgios Chatzianastasiou, George A. Constantinides:
An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics. FPL 2018: 343-350 - [c155]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - [c154]Graeme M. Bragg, Charles Leech, Domenico Balsamo, James J. Davis, Eduardo Wächter, Geoff V. Merrett, George A. Constantinides, Bashir M. Al-Hashimi:
An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems. PECCS 2018: 195-204 - 2017
- [j54]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [j53]Felix Winterstein, Kermin Elliott Fleming, Hsin-Jung Yang, George A. Constantinides:
Custom Multicache Architectures for Heap Manipulating Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 761-774 (2017) - [j52]Victor Magron, George A. Constantinides, Alastair F. Donaldson:
Certified Roundoff Error Bounds Using Semidefinite Programming. ACM Trans. Math. Softw. 43(4): 34:1-34:31 (2017) - [c153]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. ACSSC 2017: 126-130 - [c152]George Anthony Constantinides:
Algorithms and Arithmetic: Choose Wisely. ARITH 2017: 142-143 - [c151]Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Quantifying error: Extending static timing analysis with probabilistic transitions. DATE 2017: 1486-1491 - [c150]George A. Constantinides:
FPGAs in the Cloud. FPGA 2017: 167 - [c149]Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides:
Hardware Synthesis of Weakly Consistent C Concurrency. FPGA 2017: 169-178 - [c148]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - [c147]Junyi Liu, John Wickerson, George A. Constantinides:
Tile size selection for optimized memory reuse in high-level synthesis. FPL 2017: 1-8 - [c146]He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-precision constant-hardware iterative compute. FPT 2017: 73-79 - [c145]Felix Winterstein, George A. Constantinides:
Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs. FPT 2017: 104-111 - [c144]John Wickerson, Mark Batty, Tyler Sorensen, George A. Constantinides:
Automatically comparing memory consistency models. POPL 2017: 190-204 - [i5]Bulat Khusainov, Eric C. Kerrigan, Andrea Suardi, George A. Constantinides:
Nonlinear Predictive Control on a Heterogeneous Computing Platform. CoRR abs/1710.08737 (2017) - [i4]Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides:
Automatic Software and Computing Hardware Co-design for Predictive Control. CoRR abs/1710.08802 (2017) - 2016
- [j51]Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides:
Separation Logic for High-Level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(2): 10:1-10:23 (2016) - [c143]Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides:
Multi-objective Co-design for model predictive control with an FPGA. ECC 2016: 110-115 - [c142]Eric C. Kerrigan, Bulat Khusainov, George A. Constantinides:
What is different about embedded optimization? ECC 2016: 600 - [c141]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c140]Junyi Liu, John Wickerson, George A. Constantinides:
Loop Splitting for Efficient Pipelining in High-Level Synthesis. FCCM 2016: 72-79 - [c139]Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides:
A Case for Work-stealing on FPGAs with OpenCL Atomics. FPGA 2016: 48-53 - [c138]Xitong Gao, John Wickerson, George A. Constantinides:
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. FPGA 2016: 234-243 - [c137]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - [c136]Yiren Zhao, John Wickerson, George A. Constantinides:
An efficient implementation of online arithmetic. FPT 2016: 69-76 - [c135]Andrea Picciau, Gordon E. Inggs, John Wickerson, Eric C. Kerrigan, George A. Constantinides:
Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs. HiPC 2016: 183-192 - 2015
- [j50]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic. IEEE Trans. Computers 64(2): 303-315 (2015) - [j49]Abid Rafique, George A. Constantinides, Nachiket Kapre:
Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs. IEEE Trans. Parallel Distributed Syst. 26(1): 24-34 (2015) - [j48]Kan Shi, David Boland, George A. Constantinides:
Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. 8(2): 6:1-6:23 (2015) - [c134]Eric C. Kerrigan, George A. Constantinides, Andrea Suardi, Andrea Picciau, Bulat Khusainov:
Computer architectures to close the loop in real-time optimization. CDC 2015: 4597-4611 - [c133]David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica:
Transparent linking of compiled software and synthesized hardware. DATE 2015: 1084-1089 - [c132]Andrea Suardi, Eric C. Kerrigan, George A. Constantinides:
Fast FPGA prototyping toolbox for embedded optimization. ECC 2015: 2589-2594 - [c131]Junyi Liu, Samuel Bayliss, George A. Constantinides:
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. FCCM 2015: 159-162 - [c130]Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk:
Delay-Bounded Routing for Shadow Registers. FPGA 2015: 56-65 - [c129]Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides:
MATCHUP: Memory Abstractions for Heap Manipulating Programs. FPGA 2015: 136-145 - [c128]Xitong Gao, George A. Constantinides:
Numerical Program Optimization for High-Level Synthesis. FPGA 2015: 210-213 - [c127]Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica:
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA 2015: 214-217 - [c126]Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica:
PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL 2015: 1-8 - [c125]Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides:
Custom-sized caches in application-specific memory hierarchies. FPT 2015: 144-151 - [e4]George A. Constantinides, Deming Chen:
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015. ACM 2015, ISBN 978-1-4503-3315-3 [contents] - [i3]Gordon Inggs, David B. Thomas, George A. Constantinides, Wayne Luk:
Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR abs/1506.06684 (2015) - [i2]Victor Magron, George A. Constantinides, Alastair F. Donaldson:
Certified Roundoff Error Bounds Using Semidefinite Programming. CoRR abs/1507.03331 (2015) - 2014
- [j47]Stefano Longo, Eric C. Kerrigan, George A. Constantinides:
Constrained LQR for low-precision data representation. Autom. 50(1): 162-168 (2014) - [j46]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express 11(3): 20130912 (2014) - [j45]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express 11(3): 20140011 (2014) - [j44]Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari:
Embedded Online Optimization for Model Predictive Control at Megahertz Rates. IEEE Trans. Autom. Control. 59(12): 3238-3251 (2014) - [j43]Theo A. Drane, Thomas M. Rose, George A. Constantinides:
On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays. IEEE Trans. Computers 63(10): 2513-2525 (2014) - [j42]Edward Nicholas Hartley, Juan Luis Jerez, Andrea Suardi, Jan M. Maciejowski, Eric C. Kerrigan, George A. Constantinides:
Predictive Control Using an FPGA With Application to Aircraft Control. IEEE Trans. Control. Syst. Technol. 22(3): 1006-1017 (2014) - [c124]Umar Ibrahim Minhas, Samuel Bayliss, George A. Constantinides:
GPU vs FPGA: A Comparative Analysis for Non-standard Precision. ARC 2014: 298-305 - [c123]Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides:
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC 2014: 190:1-190:6 - [c122]Felix Winterstein, Samuel Bayliss, George A. Constantinides:
Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. FCCM 2014: 1-8 - [c121]Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides:
Compiling Higher Order Functional Programs to Composable Digital Hardware. FCCM 2014: 234 - [c120]Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides:
Area implications of memory partitioning for high-level synthesis on FPGAs. FPL 2014: 1-4 - [c119]Junyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides:
FPGA implementation of an interior point method for high-speed model predictive control. FPL 2014: 1-8 - [c118]Kan Shi, David Boland, George A. Constantinides:
Efficient FPGA implementation of digit parallel online arithmetic operators. FPT 2014: 115-122 - [e3]Vaughn Betz, George A. Constantinides:
The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014. ACM 2014, ISBN 978-1-4503-2671-1 [contents] - 2013
- [j41]Ammar Hasan, Eric C. Kerrigan, George A. Constantinides:
Control-Theoretic Forward Error Analysis of Iterative Numerical Algorithms. IEEE Trans. Autom. Control. 58(6): 1524-1529 (2013) - [j40]David Boland, George A. Constantinides:
A Scalable Precision Analysis Framework. IEEE Trans. Multim. 15(2): 242-256 (2013) - [c117]Stefano Longo, Eric C. Kerrigan, George A. Constantinides:
A predictive control solver for low-precision data representation. ECC 2013: 3590-3595 - [c116]Andrea Suardi, Stefano Longo, Eric C. Kerrigan, George A. Constantinides:
Energy-aware MPC co-design for DC-DC converters. ECC 2013: 3608-3613 - [c115]Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari:
Embedded Predictive Control on an FPGA using the Fast Gradient Method. ECC 2013: 3614-3620 - [c114]Kan Shi, David Boland, George A. Constantinides:
Accuracy-Performance Tradeoffs on an FPGA through Overclocking. FCCM 2013: 29-36 - [c113]Abid Rafique, Nachiket Kapre, George A. Constantinides:
Application Composition and Communication Optimization in Iterative Solvers Using FPGAs. FCCM 2013: 153-160 - [c112]David Boland, George A. Constantinides:
Word-length optimization beyond straight line code. FPGA 2013: 105-114 - [c111]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
A variation-adaptive retiming method exploiting reconfigurability. FPL 2013: 1-4 - [c110]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL 2013: 1-4 - [c109]Felix Winterstein, Samuel Bayliss, George A. Constantinides:
FPGA-based K-means clustering using tree-based data structures. FPL 2013: 1-6 - [c108]Xitong Gao, Samuel Bayliss, George A. Constantinides:
SOAP: Structural optimization of arithmetic expressions for high-level synthesis. FPT 2013: 112-119 - [c107]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT 2013: 254-261 - [c106]Felix Winterstein, Samuel Bayliss, George A. Constantinides:
High-level synthesis of dynamic data structures: A case study using Vivado HLS. FPT 2013: 362-365 - [c105]David Boland, George A. Constantinides:
Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. FPT 2013: 410-413 - [c104]Kan Shi, David Boland, George A. Constantinides:
Overclocking datapath for latency-error tradeoff. ISCAS 2013: 2537-2540 - [i1]Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari:
Embedded Online Optimization for Model Predictive Control at Megahertz Rates. CoRR abs/1303.1090 (2013) - 2012
- [j39]Juan Luis Jerez, Eric C. Kerrigan, George A. Constantinides:
A sparse and condensed QP formulation for predictive control of LTI systems. Autom. 48(5): 999-1002 (2012) - [j38]Samuel Bayliss, George A. Constantinides:
Analytical synthesis of bandwidth-efficient SDRAM address generators. Microprocess. Microsystems 36(8): 665-675 (2012) - [j37]Amir Shahzad, Eric C. Kerrigan, George A. Constantinides:
A Stable and Efficient Method for Solving a Convex Quadratic Program with Application to Optimal Control. SIAM J. Optim. 22(4): 1369-1393 (2012) - [j36]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides:
Optimizing Hardware Design by Composing Utility-Directed Transformations. IEEE Trans. Computers 61(12): 1800-1812 (2012) - [j35]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides:
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. J. Signal Process. Syst. 67(1): 65-78 (2012) - [c103]Abid Rafique, Nachiket Kapre, George A. Constantinides:
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem. ARC 2012: 239-250 - [c102]Xuan You Tan, David Boland, George A. Constantinides:
FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. ARC 2012: 290-301 - [c101]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
Towards a fixed point QP solver for predictive control. CDC 2012: 675-680 - [c100]José Gabriel F. Coutinho, Sujit Bhattacharya, Wayne Luk, George A. Constantinides, João M. P. Cardoso, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov:
Resource-Efficient Designs Using an Aspect-Oriented Approach. CSE 2012: 399-406 - [c99]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. FCCM 2012: 53-60 - [c98]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM 2012: 109-116 - [c97]David Boland, George A. Constantinides:
A scalable approach for automated precision analysis. FPGA 2012: 185-194 - [c96]Samuel Bayliss, George A. Constantinides:
Optimizing SDRAM bandwidth for custom FPGA loop accelerators. FPGA 2012: 195-204 - [c95]Abid Rafique, Nachiket Kapre, George A. Constantinides:
Enhancing performance of Tall-Skinny QR factorization using FPGAs. FPL 2012: 443-450 - [c94]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522 - [c93]Theo Drane, Wai-chuen Cheung, George A. Constantinides:
Correctly rounded constant integer division via multiply-add. ISCAS 2012: 1243-1246 - 2011
- [j34]Stefano Longo, Eric C. Kerrigan, Keck Voon Ling, George A. Constantinides:
A parallel formulation for predictive control with nonuniform hold constraints. Annu. Rev. Control. 35(2): 207-214 (2011) - [j33]Amir Shahzad, Bryn Ll. Jones, Eric C. Kerrigan, George A. Constantinides:
An efficient algorithm for the solution of a coupled Sylvester equation appearing in descriptor systems. Autom. 47(1): 244-248 (2011) - [j32]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54(1): 1-10 (2011) - [j31]George A. Constantinides, Nicola Nicolici:
Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Des. Test Comput. 28(4): 6-7 (2011) - [j30]George A. Constantinides, Adam B. Kinsman, Nicola Nicolici:
Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Des. Test Comput. 28(4): 8-17 (2011) - [j29]David Boland, George A. Constantinides:
Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1691-1704 (2011) - [j28]David Boland, George A. Constantinides:
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. ACM Trans. Reconfigurable Technol. Syst. 4(3): 22:1-22:14 (2011) - [c92]Samuel Bayliss, George A. Constantinides:
Application Specific Memory Access, Reuse and Reordering for SDRAM. ARC 2011: 41-52 - [c91]Manouk V. Manoukian, George A. Constantinides:
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations. ARC 2011: 94-101 - [c90]Christophe Le Lann, David Boland, George A. Constantinides:
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. ARC 2011: 287-295 - [c89]Stefano Longo, Eric C. Kerrigan, Keck Voon Ling, George A. Constantinides:
Parallel move blocking Model Predictive Control. CDC/ECC 2011: 1239-1244 - [c88]Ammar Hasan, Eric C. Kerrigan, George A. Constantinides:
Solving a positive definite system of linear equations via the matrix exponential. CDC/ECC 2011: 2299-2304 - [c87]Juan Luis Jerez, Eric C. Kerrigan, George A. Constantinides:
A condensed and sparse QP formulation for predictive control. CDC/ECC 2011: 5217-5222 - [c86]Theo Drane, George A. Constantinides:
Optimisation of mutually exclusive arithmetic sum-of-products. DATE 2011: 1388-1393 - [c85]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control. FPGA 2011: 209-218 - [c84]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA 2011: 284 - 2010
- [j27]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1163-1176 (2010) - [j26]Antonio Roldao Lopes, George A. Constantinides:
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices. ACM Trans. Reconfigurable Technol. Syst. 3(1): 1:1-1:19 (2010) - [j25]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 3(3): 13:1-13:21 (2010) - [j24]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator. ACM Trans. Reconfigurable Technol. Syst. 4(1): 2:1-2:21 (2010) - [j23]Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ACM Trans. Reconfigurable Technol. Syst. 4(1): 3:1-3:23 (2010) - [c83]Amir Shahzad, Eric C. Kerrigan, George A. Constantinides:
Preconditioners for inexact interior point methods for predictive control. ACC 2010: 5714-5719 - [c82]Antonio Roldao Lopes, George A. Constantinides:
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs. ARC 2010: 157-168 - [c81]David Boland, George A. Constantinides:
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. ARC 2010: 169-181 - [c80]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA. ARC 2010: 182-193 - [c79]Amir Shahzad, Eric C. Kerrigan, George A. Constantinides:
A fast well-conditioned interior point method for predictive control. CDC 2010: 508-513 - [c78]Ammar Hasan, Eric C. Kerrigan, George A. Constantinides:
An ISS and l-stability approach to forward error analysis of iterative numerical algorithms. CDC 2010: 780-785 - [c77]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides:
Customizable Composition and Parameterization of Hardware Design Transformations. DSD 2010: 595-602 - [c76]David Boland, George A. Constantinides:
Automated Precision Analysis: A Polynomial Algebraic Approach. FCCM 2010: 157-164 - [c75]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides:
A Scripting Engine for Combining Design Transformations. FCCM 2010: 255-258 - [c74]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA. FPL 2010: 89-94 - [c73]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
FPGA implementation of an interior point solver for linear model predictive control. FPT 2010: 316-319
2000 – 2009
- 2009
- [j22]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Comput. Digit. Tech. 3(3): 235-246 (2009) - [j21]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 305-315 (2009) - [j20]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung:
Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. 14(3): 39:1-39:28 (2009) - [j19]Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung:
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1(4): 24:1-24:28 (2009) - [j18]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. ACM Trans. Reconfigurable Technol. Syst. 2(4): 22:1-22:29 (2009) - [j17]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots. J. Signal Process. Syst. 56(1): 41-50 (2009) - [c72]Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung:
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144 - [c71]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator. ARC 2009: 231-242 - [c70]George A. Constantinides:
Tutorial paper: Parallel architectures for model predictive control. ECC 2009: 138-143 - [c69]Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan:
More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. FCCM 2009: 209-216 - [c68]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Area estimation and optimisation of FPGA routing fabrics. FPL 2009: 256-261 - [c67]Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides:
Optimising designs by combining model-based and pattern-based transformations. FPL 2009: 308-313 - [c66]Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung:
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61 - 2008
- [j16]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
Custom parallel caching schemes for hardware-accelerated image compression. J. Real Time Image Process. 3(4): 289-302 (2008) - [j15]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. IEEE Trans. Circuits Syst. Video Technol. 18(12): 1703-1712 (2008) - [j14]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 733-744 (2008) - [j13]George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong:
Guest Editorial: Field Programmable Technology. J. Signal Process. Syst. 51(1): 1-2 (2008) - [c65]Antonio Roldao Lopes, George A. Constantinides:
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. ARC 2008: 75-86 - [c64]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135 - [c63]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Parallel Hardware Architecture for Image Feature Detection. ARC 2008: 136-147 - [c62]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. ARC 2008: 231-242 - [c61]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. 2008: 295-304 - [c60]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184 - [c59]David Boland, George A. Constantinides:
An FPGA-based implementation of the MINRES algorithm. FPL 2008: 379-384 - [c58]Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos:
Co-optimisation of datapath and memory in outer loop pipelining. FPT 2008: 1-8 - [c57]Antonio Roldao Lopes, George A. Constantinides, Eric C. Kerrigan:
A floating-point solver for band structured linear equations. FPT 2008: 353-356 - [c56]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith:
Glitch-aware output switching activity from word-level statistics. ISCAS 2008: 1792-1795 - 2007
- [j12]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
ROM to DSP block transfer for resource constrained synthesis. IET Comput. Digit. Tech. 1(1): 17-26 (2007) - [j11]George A. Constantinides:
Special issue on Field-Programmable Technology. J. Real Time Image Process. 2(4): 177-178 (2007) - [j10]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1003-1016 (2007) - [c55]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260 - [c54]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318 - [c53]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung:
On the feasibility of early routing capacitance estimation for FPGAs. FPL 2007: 234-239 - [c52]Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL 2007: 576-579 - [c51]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. FPT 2007: 105-112 - [c50]Kwang-Hwee Seah, Michael Yan Wah Chia, Christos Papavassiliou, George A. Constantinides:
CCDF and Monte Carlo Analysis of a Digital Polar Transmitter for Ultra-Wideband System. PIMRC 2007: 1-5 - 2006
- [j9]Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides:
Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1990-2000 (2006) - [j8]Gabriel Caffarena, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras, Octavio Nieto-Taladriz:
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 339-343 (2006) - [j7]George A. Constantinides:
Word-length optimization for differentiable nonlinear systems. ACM Trans. Design Autom. Electr. Syst. 11(1): 26-43 (2006) - [c49]Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216 - [c48]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM 2006: 275-276 - [c47]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100 - [c46]Su-Shin Ang, George A. Constantinides:
Dynamic Memory Sub-System for Reconfigurable Platforms. FPL 2006: 1-2 - [c45]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6 - [c44]Jonathan A. Clarke, George A. Constantinides:
High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. FPL 2006: 1-2 - [c43]Konstantinos Masselos, George A. Constantinides, Qiang Liu:
Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. FPL 2006: 1-6 - [c42]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL 2006: 1-6 - [c41]Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong:
FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. FPL 2006: 1-6 - [c40]Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk:
An FPGA implementation of the simplex algorithm. FPT 2006: 49-56 - [c39]Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides:
PowerBit - power aware arithmetic bit-width optimization. FPT 2006: 289-292 - [c38]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT 2006: 333-336 - [c37]Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides:
Modeling of glitch effects in FPGA based arithmetic circuits. FPT 2006: 349-352 - [c36]Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung:
Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS 2006 - [c35]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176 - [e2]George A. Constantinides, Wai-Kei Mak, Phaophak Sirisuk, Theerayod Wiangtong:
2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006. IEEE 2006, ISBN 0-7803-9728-2 [contents] - 2005
- [j6]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 39-57 (2005) - [c34]Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung:
A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM 2005: 13-22 - [c33]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148 - [c32]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA 2005: 268 - [c31]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL 2005: 77-82 - [c30]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
Power and Area Optimization for Multiple Restricted Multiplication. FPL 2005: 112-117 - [c29]Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides:
Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL 2005: 124-129 - [c28]Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
Heterogeneity Exploration for Multiple 2D Filter Designs. FPL 2005: 263-268 - [c27]Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides:
FPGA-Accelerated Reconstruction of Gene Regulatory Networks. FPL 2005: 323-328 - [c26]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL 2005: 341-346 - [c25]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414 - [c24]Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides:
Parameterized Logic Power Consumption Models for FPGA based Systems. FPL 2005: 626-629 - [c23]Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung:
A novel 2D filter design methodology. ISCAS (1) 2005: 532-535 - [c22]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
A heuristic approach for multiple restricted multiplication. ISCAS (1) 2005: 692-695 - 2004
- [b1]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis and optimization of DSP algorithms. Kluwer 2004, ISBN 978-1-4020-7930-6, pp. I-XI, 1-164 - [j5]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa:
Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004) - [c21]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272 - [c20]George A. Constantinides, Abunaser Miah, Nalin Sidahao:
Word-Length Optimization of Folded Polynomial Evaluation. FCCM 2004: 285-286 - [c19]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
Migrating Functionality from ROMS to Embedded Multipliers. FCCM 2004: 287-288 - [c18]Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides:
Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL 2004: 200-208 - [c17]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
Multiple Restricted Multiplication. FPL 2004: 374-383 - [c16]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051 - 2003
- [j4]George A. Constantinides:
Review of Computer arithmetic algorithms by Israel Koren. A.K. Peters. SIGACT News 34(3): 13-15 (2003) - [j3]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Wordlength optimization for linear digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1432-1442 (2003) - [j2]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003) - [c15]George A. Constantinides:
Perturbation Analysis for Word-length Optimization. FCCM 2003: 81-90 - [c14]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615 - [c13]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
Architectures for function evaluation on FPGAs. ISCAS (2) 2003: 804-807 - [e1]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa:
Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Lecture Notes in Computer Science 2778, Springer 2003, ISBN 3-540-40822-3 [contents] - 2002
- [j1]George A. Constantinides, Gerhard J. Woeginger:
The complexity of multiple wordlength assignment. Appl. Math. Lett. 15(2): 137-140 (2002) - [c12]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum Wordlength Allocation. FCCM 2002: 219-228 - [c11]Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen:
Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456 - 2001
- [c10]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797 - [c9]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
The Multiple Wordlength Paradigm. FCCM 2001: 51-60 - 2000
- [c8]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple Precision for Resource Minimization. FCCM 2000: 307-308 - [c7]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple-Wordlength Resource Binding. FPL 2000: 646-655 - [c6]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Roundoff-noise shaping in filter design. ISCAS 2000: 57-60 - [c5]Nikos Fragoulis, Ioannis Haritantis, George A. Constantinides:
Active filter synthesis based on tuneable log-domain lossy integrators. ISCAS 2000: 409-412
1990 – 1999
- 1999
- [c4]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332 - 1991
- [c3]D. K. Mitrakos, George A. Constantinides:
Layered DCT video coding for embedded data transmission over BISDN. ICASSP 1991: 2841-2844
1980 – 1989
- 1983
- [c2]D. K. Mitrakos, George A. Constantinides:
Maximum likelihood estimation of composite source models for image coding. ICASSP 1983: 1244-1247 - 1982
- [c1]D. K. Mitrakos, George A. Constantinides:
Composite source coding techniques for image bandwidth compression. ICASSP 1982: 1223-1226
Coauthor Index
Samuel Bayliss
aka: Samuel R. Bayliss
aka: Samuel R. Bayliss
[j72] [j70] [c181] [c171] [i19] [i17] [j62] [j60] [c165] [c162] [i13] [i11] [i8] [i7] [j55] [c158] [c155] [j54] [c148] [c141] [c137] [j46] [j45] [c111] [c110] [c107] [c98] [c94] [j32] [c84] [j27] [j25] [j23] [j22] [j21] [j20] [j19] [j18] [c72] [c68] [c66] [j16] [j14] [c64] [c61] [c60] [c58] [c56] [j12] [j10] [c55] [c54] [c53] [c51] [j8] [c49] [c48] [c47] [c45] [c42] [c38] [c36] [c35] [j6] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c26] [c25] [c23] [c22] [b1] [j5] [c21] [c19] [c18] [c17] [c16] [j3] [j2] [c14] [c13] [e1] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c4]
Theo Drane
aka: Theo A. Drane
aka: Theo A. Drane
Felix Winterstein
aka: Felix J. Winterstein
aka: Felix J. Winterstein
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