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ORCID29th FCCM 2021: Orlando, FL, USA
- 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2021, Orlando, FL, USA, May 9-12, 2021. IEEE 2021, ISBN 978-1-6654-3555-0
- Matthew Hofmann
, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson, André DeHon:
XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion. 1-9 - Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich:
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. 10-19 - Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton:
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. 20-28 - Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna:
BoostGCN: A Framework for Optimizing GCN Inference on FPGA. 29-39 - Amin Kalantar, Zachary Zimmerman, Philip Brisk:
FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction. 40-49 - Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer:
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. 50-59 - Yuanfan Xu, Zhaoliang Zhang, Jincheng Yu, Jianfei Cao, Haolin Dong, Zhengfeng Huang, Yu Wang, Huazhong Yang:
GAME: Gaussian Mixture Model Mapping and Navigation Engine on Embedded FPGA. 60-68 - James Stanley Targett, Wayne Luk, Michael Lange, Olivier Marsden:
Systematically migrating an operational microphysics parameterisation to FPGA technology. 69-77 - Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco D. Santambrogio:
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design. 78-87 - Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. 88-96 - Jialiang Zhang, Nicholas Beckwith, Jing Jane Li:
GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAs. 97-105 - Weikang Qiao, Jihun Oh, Licheng Guo, Mau-Chung Frank Chang, Jason Cong:
FANS: FPGA-Accelerated Near-Storage Sorting. 106-114 - Frederick Tombs, Alireza Mellat, Nachiket Kapre:
Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs. 115-123 - Gaspar Ribeiro, Nuno Neves, Sergio Santander-Jiménez, Aleksandar Ilic:
HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection. 124-132 - Alberto Zeni, Guido Walter Di Donato, Lorenzo Di Tucci, Marco Rabozzi, Marco D. Santambrogio:
The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable Hardware. 133-141 - Chunshu Wu, Tong Geng, Sahan Bandara, Chen Yang, Vipin Sachdeva, Woody Sherman, Martin C. Herbordt:
Upgrade of FPGA Range-Limited Molecular Dynamics to Handle Hundreds of Processors. 142-151 - Linjun Qiao, Guojie Luo, Wentai Zhang, Ming Jiang:
FPGA-accelerated Iterative Reconstruction for Transmission Electron Tomography. 152-156 - Chao Jiang, David Ojika, Bhavesh Patel, Herman Lam:
Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth Memory. 157-164 - Stylianos I. Venieris, Javier Fernández-Marqués, Nicholas D. Lane:
unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation. 165-175 - Pankaj Bhowmik, Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda:
ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA. 176-180 - Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu:
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. 181-185 - Dillon Huff, Steve Dai, Pat Hanrahan:
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs. 186-194 - Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Scheduling in High-Level Synthesis. 195-203 - Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. 204-213 - Eric Micallef, Yuanlong Xiao, André DeHon:
HLS-Compatible, Embedded-Processor Stream Links. 214-218 - Yann Herklotz, Zewei Du, Nadesh Ramanathan, John Wickerson:
An Empirical Study of the Reliability of High-Level Synthesis Tools. 219-223 - Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong, Jakub Szefer:
Cloud FPGA Cartography using PCIe Contention. 224-232 - Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi, Nele Mentens:
Trusted Configuration in Cloud FPGAs. 233-241 - Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, Russell Tessier, Jakub Szefer:
Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs. 242-246 - Zhenyu Xu, Thomas Mauldin, Qing Yang, Tao Wei:
Runtime Detection of Probing/Tampering on Interconnecting Buses. 247-251 - Feng Yu, He Li, Rongshi Dai, Yongming Tang:
A General Video Processing Framework on Edge Computing FPGAs. 252 - Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond:
A Tunable Dual-Edge Time-to-Digital Converter. 253 - Ji-Hoon Kim, Yeo-Reum Park, Jaeyoung Do, Soo Young Ji, Joo-Young Kim:
Accelerating Large-Scale Nearest Neighbor Search with Computational Storage Device. 254 - Sanjay Gandham, Rakin Muhammad Shadab, Mingjie Lin:
ARC: Reconfigurable Cache Security Assurance with Application-Specific Randomized Mapping in FPGA-Based Heterogeneous Computing. 255 - Yanze Li, Yufan Zhang, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu:
AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design. 256 - Daniele Passaretti, Thilo Pionteck:
Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography. 257 - Jan Kubálek, Jakub Cabal, Martin Spinler, Radek Isa:
DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers. 258 - Duvindu Piyasena, Siew-Kei Lam, Meiqing Wu:
Edge Accelerator for Lifelong Deep Learning using Streaming Linear Discriminant Analysis. 259 - Ramon Nepomuceno, Renan Sterle, Guilherme Valarini, Márcio Machado Pereira, Hervé Yviquel, Guido Araujo:
Enabling OpenMP Task Parallelism on Multi-FPGAs. 260 - Chengyue Wang, Sitao Huang, Wen-Mei Hwu, Deming Chen:
Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design. 261 - Yu Zou, Mingjie Lin:
FERMAT: FPGA-Accelerated Heterogeneous Computing Platform Near NVMe Storage. 262 - Juan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow:
FFIVE: An FPGA Framework for Interactive VNF Environments. 263 - Tiandong Zhao, Yunxuan Yu, Kun Wang, Lei He:
Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs. 264 - Mohammadreza Soltaniyeh, Veronica Lagrange Moutinho dos Reis, Matthew Bryson, Richard P. Martin, Santosh Nagarakatte:
Near-Storage Acceleration of Database Query Processing with SmartSSDs. 265 - Mahdi Nazemi, Arash Fayyazi, Amirhossein Esmaili, Atharva Khare, Soheil Nazar Shahsavani, Massoud Pedram:
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic. 266-267 - C. N. Ramachandra, Anirban Nag, Rajeev Balasubramonian, Gurpreet S. Kalsi, Kamlesh R. Pillai, Sreenivas Subramoney:
ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis. 268-269 - Lawrence C. Stewart, Carlo Pascoe, Emery Davis, Brian W. Sherman, Martin C. Herbordt, Vipin Sachdeva:
Particle Mesh Ewald for Molecular Dynamics in OpenCL on an FPGA Cluster. 270 - Arzhang Rafii, Paul Chow, Welson Sun:
Pharos: a Performance Monitor for Multi-FPGA Systems. 271 - Ameer M. S. Abdelhadi, He Li:
Reconfigurable Synthesizable Synchronization FIFOs. 272 - Oscar Rahnama, Stuart Golodetz, Tommaso Cavallari, Philip H. S. Torr:
Scalable FPGA Median Filtering via a Directional Median Cascade. 273 - Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. 274 - Zhengzheng Ma, Guojie Luo:
TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths. 275 - Hyunmin Jeong, Deming Chen:
TwinDNN: A Tale of Two Deep Neural Networks. 276 - Evangelos Mageiropoulos, Nikolaos Chrysos, Nikolaos Dimou, Manolis Katevenis:
Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices. 277 - Verjina Torosian Khouygani, Shahnam Mirzaei, Christian Beck, Debi Prasad Choudhary:
An FPGA Based Hardware Accelerated Framework for Solar Spectra Matching with Parameterized Matched Filter IP Core. 278 - Yanran P. Chen, Martin L. Voogel, Ed Priest, Qian Wang, Ranjeeth Doppalapudi, Praful Jain:
Time-Domain FPGA Power Delivery Network Characterization Methodology. 279
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